Message ID | 20211112081003.15453-5-biju.das.jz@bp.renesas.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Geert Uytterhoeven |
Headers | show |
Series | Add OPP table for RZ/G2L SoC | expand |
Hi Biju, On Fri, Nov 12, 2021 at 9:10 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add OPP table for RZ/G2L SoC. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > V1->v2: > * Fixed typo cluster1_opp->cluster0_opp Thanks for the update! > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > @@ -42,6 +42,32 @@ > clock-frequency = <0>; > }; > > + cluster0_opp: opp_table { "make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/opp/opp-v2.yaml" doesn't like the node name. The rest looks good to me. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH v2 4/4] arm64: dts: renesas: r9a07g044: Add OPP table > > Hi Biju, > > On Fri, Nov 12, 2021 at 9:10 AM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > Add OPP table for RZ/G2L SoC. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > V1->v2: > > * Fixed typo cluster1_opp->cluster0_opp > > Thanks for the update! > > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > @@ -42,6 +42,32 @@ > > clock-frequency = <0>; > > }; > > > > + cluster0_opp: opp_table { > > "make dtbs_check > DT_SCHEMA_FILES=Documentation/devicetree/bindings/opp/opp-v2.yaml" > doesn't like the node name. OK, Will check and send the fix as v3 for this patch. Regards, Biju
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 43a5d359519a..ccb788de6654 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -42,6 +42,32 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -63,6 +89,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -71,6 +99,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 {