diff mbox series

[3/3] arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK

Message ID 20211216114305.5842-4-biju.das.jz@bp.renesas.com (mailing list archive)
State Accepted
Delegated to: Geert Uytterhoeven
Headers show
Series Add Renesas RZ/G2LC{SoC,SMARC EVK} support | expand

Commit Message

Biju Das Dec. 16, 2021, 11:43 a.m. UTC 
Add basic support for RZ/G2LC SMARC EVK (based on R9A07G044C2):
- memory
- External input clock
- SCIF
- GbEthernet
- Audio Clock

It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which is not tested and
delete the corresponding pinctrl definitions.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  1 +
 .../boot/dts/renesas/r9a07g044c2-smarc.dts    | 99 +++++++++++++++++++
 .../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 25 +++++
 .../boot/dts/renesas/rzg2lc-smarc-som.dtsi    | 76 ++++++++++++++
 4 files changed, 201 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi

Comments

Geert Uytterhoeven Jan. 10, 2022, 2:53 p.m. UTC | #1 
Hi Biju,

On Thu, Dec 16, 2021 at 12:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add basic support for RZ/G2LC SMARC EVK (based on R9A07G044C2):
> - memory
> - External input clock
> - SCIF
> - GbEthernet
> - Audio Clock
>
> It shares the same carrier board with RZ/G2L, but the pin mapping is
> different. Disable the device nodes which is not tested and
> delete the corresponding pinctrl definitions.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Before I queue this in renesas-devel for v5.18, I have two questions:

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/G2LC SMARC EVK board
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +#include "r9a07g044c2.dtsi"
> +#include "rzg2lc-smarc-som.dtsi"
> +#include "rzg2lc-smarc-pinfunction.dtsi"

1) So far it looks like the definitions in rzg2lc-smarc-pinfunction.dtsi
   do not really differ from those in rzg2l-smarc-pinfunction.dtsi,\
   there are just less. Will there be other differences?
2) Would it make sense to create rzg2*-smarc-som-pinfunction.dtsi
   files, too?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Biju Das Jan. 10, 2022, 5:28 p.m. UTC | #2 
Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH 3/3] arm64: dts: renesas: Add initial device tree for
> RZ/G2LC SMARC EVK
> 
> Hi Biju,
> 
> On Thu, Dec 16, 2021 at 12:43 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add basic support for RZ/G2LC SMARC EVK (based on R9A07G044C2):
> > - memory
> > - External input clock
> > - SCIF
> > - GbEthernet
> > - Audio Clock
> >
> > It shares the same carrier board with RZ/G2L, but the pin mapping is
> > different. Disable the device nodes which is not tested and delete the
> > corresponding pinctrl definitions.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Thanks for your patch!
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Before I queue this in renesas-devel for v5.18, I have two questions:
> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
> > @@ -0,0 +1,99 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/G2LC SMARC EVK board
> > + *
> > + * Copyright (C) 2021 Renesas Electronics Corp.
> > + */
> > +
> > +/dts-v1/;
> > +#include "r9a07g044c2.dtsi"
> > +#include "rzg2lc-smarc-som.dtsi"
> > +#include "rzg2lc-smarc-pinfunction.dtsi"
> 
> 1) So far it looks like the definitions in rzg2lc-smarc-pinfunction.dtsi
>    do not really differ from those in rzg2l-smarc-pinfunction.dtsi,\
>    there are just less. Will there be other differences?

SoM module contains below SW for multiplex function. Same pins used for both operations.

SW1-3 : 1:CAN1, 0:SCIF1
SW1-4 : 1:CAN1, 0:RSPI1
SW1-5 : 1:I2S2 HDMI Audio, 0:I2S0 Audio code

Apart from this, there are differences w.r.to 
1) PMOD pins
2) SD0 power enable and SD0_DEV_SEL
3) IIC3
4) Only CAN1 and ETH0.

> 2) Would it make sense to create rzg2*-smarc-som-pinfunction.dtsi
>    files, too?

Only ADC, Ethernet and SD0/eMMC are defined on SoM.

Between RZ/G2L and RZ/G2LC, ADC is not present on LC
And SD0 pins are different between this as mentioned above.

Only ethernet(eth0) is common, but that also different in RZ/G2UL.
That is the reason it is not done.

If there is a value in adding, rzg2*-smarc-som-pinfunction.dtsi, I can create
rzg2*-smarc-som-pinfunction.dtsi files. 

Please let me know.

Regards,
Biju
Geert Uytterhoeven Jan. 10, 2022, 5:41 p.m. UTC | #3 
Hi Biju,

On Mon, Jan 10, 2022 at 6:28 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Geert,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH 3/3] arm64: dts: renesas: Add initial device tree for
> > RZ/G2LC SMARC EVK
> >
> > Hi Biju,
> >
> > On Thu, Dec 16, 2021 at 12:43 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > Add basic support for RZ/G2LC SMARC EVK (based on R9A07G044C2):
> > > - memory
> > > - External input clock
> > > - SCIF
> > > - GbEthernet
> > > - Audio Clock
> > >
> > > It shares the same carrier board with RZ/G2L, but the pin mapping is
> > > different. Disable the device nodes which is not tested and delete the
> > > corresponding pinctrl definitions.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > Before I queue this in renesas-devel for v5.18, I have two questions:
> >
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
> > > @@ -0,0 +1,99 @@
> > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +/*
> > > + * Device Tree Source for the RZ/G2LC SMARC EVK board
> > > + *
> > > + * Copyright (C) 2021 Renesas Electronics Corp.
> > > + */
> > > +
> > > +/dts-v1/;
> > > +#include "r9a07g044c2.dtsi"
> > > +#include "rzg2lc-smarc-som.dtsi"
> > > +#include "rzg2lc-smarc-pinfunction.dtsi"
> >
> > 1) So far it looks like the definitions in rzg2lc-smarc-pinfunction.dtsi
> >    do not really differ from those in rzg2l-smarc-pinfunction.dtsi,\
> >    there are just less. Will there be other differences?
>
> SoM module contains below SW for multiplex function. Same pins used for both operations.
>
> SW1-3 : 1:CAN1, 0:SCIF1
> SW1-4 : 1:CAN1, 0:RSPI1
> SW1-5 : 1:I2S2 HDMI Audio, 0:I2S0 Audio code
>
> Apart from this, there are differences w.r.to
> 1) PMOD pins
> 2) SD0 power enable and SD0_DEV_SEL
> 3) IIC3
> 4) Only CAN1 and ETH0.

OK, so let's go as you proposed.

> > 2) Would it make sense to create rzg2*-smarc-som-pinfunction.dtsi
> >    files, too?
>
> Only ADC, Ethernet and SD0/eMMC are defined on SoM.
>
> Between RZ/G2L and RZ/G2LC, ADC is not present on LC
> And SD0 pins are different between this as mentioned above.
>
> Only ethernet(eth0) is common, but that also different in RZ/G2UL.
> That is the reason it is not done.
>
> If there is a value in adding, rzg2*-smarc-som-pinfunction.dtsi, I can create
> rzg2*-smarc-som-pinfunction.dtsi files.
>
> Please let me know.

Thanks, it's fine as-is.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 5bc8065a7864..8e696a38c560 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -76,3 +76,4 @@  dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
 
 dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
new file mode 100644
index 000000000000..53845823d0dc
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -0,0 +1,99 @@ 
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044c2.dtsi"
+#include "rzg2lc-smarc-som.dtsi"
+#include "rzg2lc-smarc-pinfunction.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+	model = "Renesas SMARC EVK based on r9a07g044c2";
+	compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
+
+};
+
+&canfd {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&ehci0 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&ehci1 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&hsusb {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&i2c0 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&i2c1 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&i2c3 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&ohci0 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&ohci1 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&phyrst {
+	status = "disabled";
+};
+
+&scif2 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&sdhi1 {
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-1;
+	/delete-property/ vmmc-supply;
+	status = "disabled";
+};
+
+&spi1 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&ssi0 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&usb2_phy0 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
+
+&usb2_phy1 {
+	/delete-property/ pinctrl-0;
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
new file mode 100644
index 000000000000..5333a1f9a0e7
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -0,0 +1,25 @@ 
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC pincontrol parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+&pinctrl {
+	pinctrl-0 = <&sound_clk_pins>;
+	pinctrl-names = "default";
+
+	scif0_pins: scif0 {
+		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
+			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
+	};
+
+	sound_clk_pins: sound_clk {
+		pins = "AUDIO_CLK1", "AUDIO_CLK2";
+		input-enable;
+	};
+};
+
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
new file mode 100644
index 000000000000..e1d7a3a689c6
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -0,0 +1,76 @@ 
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC SOM common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/ {
+	aliases {
+		ethernet0 = &eth0;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
+	};
+};
+
+&eth0 {
+	pinctrl-0 = <&eth0_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+
+	phy0: ethernet-phy@7 {
+		compatible = "ethernet-phy-id0022.1640",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <7>;
+		rxc-skew-psec = <2400>;
+		txc-skew-psec = <2400>;
+		rxdv-skew-psec = <0>;
+		txdv-skew-psec = <0>;
+		rxd0-skew-psec = <0>;
+		rxd1-skew-psec = <0>;
+		rxd2-skew-psec = <0>;
+		rxd3-skew-psec = <0>;
+		txd0-skew-psec = <0>;
+		txd1-skew-psec = <0>;
+		txd2-skew-psec = <0>;
+		txd3-skew-psec = <0>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <24000000>;
+};
+
+&pinctrl {
+	eth0_pins: eth0 {
+		pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+			 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+			 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+			 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+			 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+			 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+			 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+			 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+			 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+			 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+			 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+			 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+	};
+};
+