| Message ID | 20220204161806.3126321-5-jjhiblot@traphandler.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | ARM: r9a06g032: add support for the watchdogs | expand |
Hi Jean-Jacques, On Fri, Feb 4, 2022 at 5:18 PM Jean-Jacques Hiblot <jjhiblot@traphandler.com> wrote: > This SOC includes 2 watchdog controllers (one per A7 core). > > Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Thanks for your patch! > --- a/arch/arm/boot/dts/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > @@ -184,6 +184,22 @@ gic: interrupt-controller@44101000 { > interrupts = > <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > }; > + > + wdt0: watchdog@40008000 { Please insert these nodes before the system-controller@4000c000 node, to preserve sort order (by unit address). > + compatible = "renesas,rzn1-wdt"; "renesas,r9a06g032-wdt", "renesas,rzn1-wdt" as per my comments on the DT bindings patch. > + reg = <0x40008000 0x1000>; > + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; > + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; > + status = "disabled"; > + }; > + > + wdt1: watchdog@40009000 { > + compatible = "renesas,rzn1-wdt"; > + reg = <0x40009000 0x1000>; > + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; > + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; > + status = "disabled"; > + }; > }; > Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index c47896e4ab58..54c91b46a5d0 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -184,6 +184,22 @@ gic: interrupt-controller@44101000 { interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; + + wdt0: watchdog@40008000 { + compatible = "renesas,rzn1-wdt"; + reg = <0x40008000 0x1000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + + wdt1: watchdog@40009000 { + compatible = "renesas,rzn1-wdt"; + reg = <0x40009000 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; }; timer {
This SOC includes 2 watchdog controllers (one per A7 core). Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> --- arch/arm/boot/dts/r9a06g032.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)