| Message ID | 20220222103437.194779-8-miquel.raynal@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | RZN1 DMA support | expand |
Hi Miquel, On Tue, Feb 22, 2022 at 11:35 AM Miquel Raynal <miquel.raynal@bootlin.com> wrote: > Describe the two DMA controllers available on this SoC. > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Thanks for your patch! > --- a/arch/arm/boot/dts/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > @@ -184,6 +184,36 @@ nand_controller: nand-controller@40102000 { > status = "disabled"; > }; > > + dma0: dma-controller@40104000 { > + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; > + reg = <0x40104000 0x1000>; > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "hclk"; > + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; power-domains? > + dma-channels = <8>; > + dma-requests = <16>; > + dma-masters = <1>; > + #dma-cells = <3>; <4>? The dmamux bindings say: + The first four cells are dedicated to the master DMA controller. The fifth + cell gives the DMA mux bit index that must be set starting from 0. The + sixth cell gives the binary value that must be written there, ie. 0 or 1. > + block_size = <0xfff>; > + data_width = <3>; > + status = "disabled"; > + }; The rest LGTM. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, geert@linux-m68k.org wrote on Wed, 23 Feb 2022 13:54:20 +0100: > Hi Miquel, > > On Tue, Feb 22, 2022 at 11:35 AM Miquel Raynal > <miquel.raynal@bootlin.com> wrote: > > Describe the two DMA controllers available on this SoC. > > > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > > Thanks for your patch! > > > --- a/arch/arm/boot/dts/r9a06g032.dtsi > > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > > @@ -184,6 +184,36 @@ nand_controller: nand-controller@40102000 { > > status = "disabled"; > > }; > > > > + dma0: dma-controller@40104000 { > > + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; > > + reg = <0x40104000 0x1000>; > > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > > + clock-names = "hclk"; > > + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; > > power-domains? > > > + dma-channels = <8>; > > + dma-requests = <16>; > > + dma-masters = <1>; > > + #dma-cells = <3>; > > <4>? The dmamux bindings say: > > + The first four cells are dedicated to the master DMA > controller. The fifth > + cell gives the DMA mux bit index that must be set starting from 0. The > + sixth cell gives the binary value that must be written there, ie. 0 or 1. The DMAC bindings had initially 3 cells, and then received a fourth optional one. We do not need it here, that's why I'm keeping #dma-cells to 3. But on the mux side, I don't want to deal with the presence or absence of the optional cell so I assumed we would always request 4 cells for the DMAC to be on the safe side. Is this assumption wrong? Thanks, Miquèl
Hi Miquel, On Wed, Feb 23, 2022 at 6:14 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote: > geert@linux-m68k.org wrote on Wed, 23 Feb 2022 13:54:20 +0100: > > On Tue, Feb 22, 2022 at 11:35 AM Miquel Raynal > > <miquel.raynal@bootlin.com> wrote: > > > Describe the two DMA controllers available on this SoC. > > > > > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > > > > Thanks for your patch! > > > > > --- a/arch/arm/boot/dts/r9a06g032.dtsi > > > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > > > @@ -184,6 +184,36 @@ nand_controller: nand-controller@40102000 { > > > status = "disabled"; > > > }; > > > > > > + dma0: dma-controller@40104000 { > > > + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; > > > + reg = <0x40104000 0x1000>; > > > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > > > + clock-names = "hclk"; > > > + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; > > > > power-domains? > > > > > + dma-channels = <8>; > > > + dma-requests = <16>; > > > + dma-masters = <1>; > > > + #dma-cells = <3>; > > > > <4>? The dmamux bindings say: > > > > + The first four cells are dedicated to the master DMA > > controller. The fifth > > + cell gives the DMA mux bit index that must be set starting from 0. The > > + sixth cell gives the binary value that must be written there, ie. 0 or 1. > > The DMAC bindings had initially 3 cells, and then received a fourth > optional one. We do not need it here, that's why I'm keeping #dma-cells > to 3. > > But on the mux side, I don't want to deal with the presence or absence > of the optional cell so I assumed we would always request 4 cells for > the DMAC to be on the safe side. > > Is this assumption wrong? OK. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index db657224688a..640c3eb4bbcd 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -184,6 +184,36 @@ nand_controller: nand-controller@40102000 { status = "disabled"; }; + dma0: dma-controller@40104000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40104000 0x1000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data_width = <3>; + status = "disabled"; + }; + + dma1: dma-controller@40105000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40105000 0x1000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA1>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data_width = <3>; + status = "disabled"; + }; + gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller;
Describe the two DMA controllers available on this SoC. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- arch/arm/boot/dts/r9a06g032.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)