| Message ID | 20220401124523.42892-1-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | mmc: renesas_sdhi: special 4tap settings only apply to HS400 | expand |
Hi Wolfram-san, Thank you for the patch! > From: Wolfram Sang, Sent: Friday, April 1, 2022 9:45 PM > > Previous doucmentation was vague, so we included SDR104 for slow SDnH s/doucmentation/documentation/ > clock settings. It turns out now, that it is only needed for HS400. > > Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") > Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> After fixed the typo, Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Best regards, Yoshihiro Shimoda
> > Previous doucmentation was vague, so we included SDR104 for slow SDnH > > s/doucmentation/documentation/ Oops, thank you! v2 sent out now.
Hi Wolfram, On Fri, Apr 1, 2022 at 11:49 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Previous doucmentation was vague, so we included SDR104 for slow SDnH > clock settings. It turns out now, that it is only needed for HS400. > > Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") > Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> (after fixing the typo) Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- a/drivers/mmc/host/renesas_sdhi_core.c > +++ b/drivers/mmc/host/renesas_sdhi_core.c > @@ -144,9 +144,9 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, > return clk_get_rate(priv->clk); > > if (priv->clkh) { > + /* HS400 with 4TAP needs different clock settings */ > bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; > - bool need_slow_clkh = (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) || > - (host->mmc->ios.timing == MMC_TIMING_MMC_HS400); > + bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; I'm wondering if we've lost the critical mass for keeping the bools? > clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; Unfortunately I don't see a good way to rewrite this, without inflating source code size... > ref_clk = priv->clkh; > } Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
> > bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; > > - bool need_slow_clkh = (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) || > > - (host->mmc->ios.timing == MMC_TIMING_MMC_HS400); > > + bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; > > I'm wondering if we've lost the critical mass for keeping the bools? Might be. I'll think about it.
> I'm wondering if we've lost the critical mass for keeping the bools?
So, I had a look at this and think that the current version is still way
better in terms of readability. I think the compilers will optimize
enough. It is not a hot path anyway. So, I'd like to keep the code.
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 2797a9c0f17d..2a4d314aa027 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -144,9 +144,9 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, return clk_get_rate(priv->clk); if (priv->clkh) { + /* HS400 with 4TAP needs different clock settings */ bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; - bool need_slow_clkh = (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) || - (host->mmc->ios.timing == MMC_TIMING_MMC_HS400); + bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; ref_clk = priv->clkh; }
Previous doucmentation was vague, so we included SDR104 for slow SDnH clock settings. It turns out now, that it is only needed for HS400. Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- drivers/mmc/host/renesas_sdhi_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)