diff mbox series

clk: renesas: rzg2l: Fix duplicate argument in rzg2l-cpg

Message ID 20220504142058.18704-1-wanjiabing@vivo.com (mailing list archive)
State Accepted
Delegated to: Geert Uytterhoeven
Headers show
Series clk: renesas: rzg2l: Fix duplicate argument in rzg2l-cpg | expand

Commit Message

Jiabing Wan May 4, 2022, 2:20 p.m. UTC
Fix following coccicheck warning:
./drivers/clk/renesas/rzg2l-cpg.c:603:39-65: duplicated argument to & or |

The CPG_SIPLL5_CLK1_REFDIV_WEN here is duplicated.
Here should be CPG_SIPLL5_CLK1_POSTDIV2_WEN.

Fixes: a16ed737e62b ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
Signed-off-by: Wan Jiabing <wanjiabing@vivo.com>
---
 drivers/clk/renesas/rzg2l-cpg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Geert Uytterhoeven May 5, 2022, 6:52 a.m. UTC | #1
Hi Wan,

On Wed, May 4, 2022 at 4:21 PM Wan Jiabing <wanjiabing@vivo.com> wrote:
> Fix following coccicheck warning:
> ./drivers/clk/renesas/rzg2l-cpg.c:603:39-65: duplicated argument to & or |
>
> The CPG_SIPLL5_CLK1_REFDIV_WEN here is duplicated.
> Here should be CPG_SIPLL5_CLK1_POSTDIV2_WEN.

Thanks, nice catch!

> Fixes: a16ed737e62b ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
> Signed-off-by: Wan Jiabing <wanjiabing@vivo.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
As I haven't sent a pull request yet, I will fix up the original commit in
renesas-clk-for-v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 15412cc58337..a1e1fee9f483 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -600,7 +600,7 @@  static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
 	}
 
 	/* Output clock setting 1 */
-	writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_REFDIV_WEN |
+	writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_POSTDIV2_WEN |
 	       CPG_SIPLL5_CLK1_REFDIV_WEN  | (params.pl5_postdiv1 << 0) |
 	       (params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8),
 	       priv->base + CPG_SIPLL5_CLK1);