From patchwork Mon May 9 14:24:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 12843652 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AB3BC433F5 for ; Mon, 9 May 2022 14:25:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237165AbiEIO3I (ORCPT ); Mon, 9 May 2022 10:29:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237198AbiEIO3H (ORCPT ); Mon, 9 May 2022 10:29:07 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 52BFE1EF0B5; Mon, 9 May 2022 07:25:09 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,211,1647270000"; d="scan'208";a="120391087" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 09 May 2022 23:25:08 +0900 Received: from localhost.localdomain (unknown [10.226.93.110]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4126C40083CF; Mon, 9 May 2022 23:25:04 +0900 (JST) From: Phil Edworthy To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Phil Edworthy , Geert Uytterhoeven , Sergey Shtylyov , Biju Das , Lad Prabhakar , netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 2/5] ravb: Separate handling of irq enable/disable regs into feature Date: Mon, 9 May 2022 15:24:28 +0100 Message-Id: <20220509142431.24898-3-phil.edworthy@renesas.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220509142431.24898-1-phil.edworthy@renesas.com> References: <20220509142431.24898-1-phil.edworthy@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Currently, when the HW has a single interrupt, the driver uses the GIC, TIC, RIC0 registers to enable and disable interrupts. When the HW has multiple interrupts, it uses the GIE, GID, TIE, TID, RIE0, RID0 registers. However, other devices, e.g. RZ/V2M, have multiple irqs and only have the GIC, TIC, RIC0 registers. Therefore, split this into a separate feature. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das --- v2: - Renamed irq_en_dis_regs to irq_en_dis - Squashed use of GIC reg versus GIE/GID into this patch and got rid of separate gptp_ptm_gic feature. - Minor editing of the commit msg --- drivers/net/ethernet/renesas/ravb.h | 1 + drivers/net/ethernet/renesas/ravb_main.c | 5 +++-- drivers/net/ethernet/renesas/ravb_ptp.c | 4 ++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 08062d73df10..0ec8256f7eef 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -1027,6 +1027,7 @@ struct ravb_hw_info { unsigned tx_counters:1; /* E-MAC has TX counters */ unsigned carrier_counters:1; /* E-MAC has carrier counters */ unsigned multi_irqs:1; /* AVB-DMAC and E-MAC has multiple irqs */ + unsigned irq_en_dis_regs:1; /* Has separate irq enable and disable regs */ unsigned gptp:1; /* AVB-DMAC has gPTP support */ unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */ unsigned nc_queues:1; /* AVB-DMAC has RX and TX NC queues */ diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 525d66f71f02..5f45c8d68f11 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1124,7 +1124,7 @@ static bool ravb_queue_interrupt(struct net_device *ndev, int q) if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { if (napi_schedule_prep(&priv->napi[q])) { /* Mask RX and TX interrupts */ - if (!info->multi_irqs) { + if (!info->irq_en_dis_regs) { ravb_write(ndev, ric0 & ~BIT(q), RIC0); ravb_write(ndev, tic & ~BIT(q), TIC); } else { @@ -1306,7 +1306,7 @@ static int ravb_poll(struct napi_struct *napi, int budget) /* Re-enable RX/TX interrupts */ spin_lock_irqsave(&priv->lock, flags); - if (!info->multi_irqs) { + if (!info->irq_en_dis_regs) { ravb_modify(ndev, RIC0, mask, mask); ravb_modify(ndev, TIC, mask, mask); } else { @@ -2410,6 +2410,7 @@ static const struct ravb_hw_info ravb_gen3_hw_info = { .internal_delay = 1, .tx_counters = 1, .multi_irqs = 1, + .irq_en_dis_regs = 1, .ccc_gac = 1, .nc_queues = 1, .magic_pkt = 1, diff --git a/drivers/net/ethernet/renesas/ravb_ptp.c b/drivers/net/ethernet/renesas/ravb_ptp.c index c099656dd75b..a7726c2ed594 100644 --- a/drivers/net/ethernet/renesas/ravb_ptp.c +++ b/drivers/net/ethernet/renesas/ravb_ptp.c @@ -254,7 +254,7 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp, error = ravb_ptp_update_compare(priv, (u32)start_ns); if (!error) { /* Unmask interrupt */ - if (!info->multi_irqs) + if (!info->irq_en_dis_regs) ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME); else ravb_write(ndev, GIE_PTMS0, GIE); @@ -266,7 +266,7 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp, perout->period = 0; /* Mask interrupt */ - if (!info->multi_irqs) + if (!info->irq_en_dis_regs) ravb_modify(ndev, GIC, GIC_PTME, 0); else ravb_write(ndev, GID_PTMD0, GID);