diff mbox series

[4/7] v4l: vsp1: Add CLK_CTRL and MRESET register definitions

Message ID 20220629105135.2652773-5-kieran.bingham+renesas@ideasonboard.com (mailing list archive)
State New
Delegated to: Kieran Bingham
Headers show
Series renesas: vsp1: debugfs facility | expand

Commit Message

Kieran Bingham June 29, 2022, 10:51 a.m. UTC 
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
---
 .../media/platform/renesas/vsp1/vsp1_debugfs.c   | 10 ++++++++++
 drivers/media/platform/renesas/vsp1/vsp1_regs.h  | 16 ++++++++++++++++
 2 files changed, 26 insertions(+)
diff mbox series

Patch

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_debugfs.c b/drivers/media/platform/renesas/vsp1/vsp1_debugfs.c
index 4e361fd4c445..3bae9556f38b 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_debugfs.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_debugfs.c
@@ -107,10 +107,20 @@  static const struct debugfs_reg32 vsp1_regset[] = {
 	VSP1_DBFS_REG(VI6_CMD(0)),
 	VSP1_DBFS_REG(VI6_CMD(1)),
 
+	VSP1_DBFS_REG(VI6_CLK_CTRL0),
+	VSP1_DBFS_REG(VI6_CLK_CTRL1),
+
 	VSP1_DBFS_REG(VI6_CLK_DCSWT),
 
+	VSP1_DBFS_REG(VI6_CLK_DCSM0),
+	VSP1_DBFS_REG(VI6_CLK_DCSM1),
+
 	VSP1_DBFS_REG(VI6_SRESET),
 
+	VSP1_DBFS_REG(VI6_MRESET_ENB0),
+	VSP1_DBFS_REG(VI6_MRESET_ENB1),
+	VSP1_DBFS_REG(VI6_MRESET),
+
 	VSP1_DBFS_REG_DECODE(VI6_STATUS, decode_vi6_status),
 
 	VSP1_DBFS_REG_DECODE(VI6_WPF_IRQ_ENB(0), decode_vi6_wpf_enb),
diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
index 632c43bb4cbd..86855b34dcaf 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
+++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
@@ -18,15 +18,31 @@ 
 #define VI6_CMD_UPDHDR			BIT(4)
 #define VI6_CMD_STRCMD			BIT(0)
 
+#define VI6_CLK_CTRL0			0x0010
+#define VI6_CLK_CTRL1			0x0014
+
 #define VI6_CLK_DCSWT			0x0018
 #define VI6_CLK_DCSWT_CSTPW_MASK	(0xff << 8)
 #define VI6_CLK_DCSWT_CSTPW_SHIFT	8
 #define VI6_CLK_DCSWT_CSTRW_MASK	(0xff << 0)
 #define VI6_CLK_DCSWT_CSTRW_SHIFT	0
 
+#define VI6_CLK_DCSM0			0x001c
+#define VI6_CLK_DCSM1			0x0020
+
 #define VI6_SRESET			0x0028
 #define VI6_SRESET_SRTS(n)		BIT(n)
 
+#define VI6_MRESET_ENB0			0x002c
+#define VI6_MRESET_ENB0_RESET		0x0000001f
+#define VI6_MRESET_ENB0_RESET_BUS	0x30000f1f
+
+#define VI6_MRESET_ENB1			0x0030
+#define VI6_MRESET_ENB1_RESET		0xff00ffff
+
+#define VI6_MRESET			0x0034
+#define VI6_MRESET_MRST			BIT(0)
+
 #define VI6_STATUS			0x0038
 #define VI6_STATUS_FLD_STD(n)		BIT((n) + 28)
 #define VI6_STATUS_SYS_ACT(n)		BIT((n) + 8)