| Message ID | 20220630100241.35233-5-samuel@sholland.org (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow | expand |
Reviewed-by: Guo Ren <guoren@kernel.org> On Thu, Jun 30, 2022 at 6:02 PM Samuel Holland <samuel@sholland.org> wrote: > > The T-HEAD PLIC ignores additional edges seen while an edge-triggered > interrupt is being handled. Because of this behavior, the driver needs > to complete edge-triggered interrupts in the .irq_ack callback before > handling them, instead of in the .irq_eoi callback afterward. Otherwise, > it could miss some interrupts. > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > Changes in v3: > - Rebased on top of the RZ/Five patches > > drivers/irqchip/irq-sifive-plic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > index 90e44367bee9..b3a36dca7f1b 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -474,7 +474,6 @@ static int __init plic_init(struct device_node *node, > > IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); > IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ > -IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */ > > static int __init plic_edge_init(struct device_node *node, > struct device_node *parent) > @@ -483,3 +482,4 @@ static int __init plic_edge_init(struct device_node *node, > } > > IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init); > +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init); > -- > 2.35.1 >
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 90e44367bee9..b3a36dca7f1b 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -474,7 +474,6 @@ static int __init plic_init(struct device_node *node, IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ -IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */ static int __init plic_edge_init(struct device_node *node, struct device_node *parent) @@ -483,3 +482,4 @@ static int __init plic_edge_init(struct device_node *node, } IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init); +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);