| Message ID | 20220710115248.190280-3-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 4591c760b79759849b563605132e6afdd0149717 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add support for RZ/N1 SJA1000 CAN controller | expand |
On 10/07/2022 13:52, Biju Das wrote: > Add CAN binding documentation for Renesas RZ/N1 SoC. > > The SJA1000 CAN controller on RZ/N1 SoC has some differences compared > to others like it has no clock divider register (CDR) support and it has > no HW loopback (HW doesn't see tx messages on rx), so introduced a new > compatible 'renesas,rzn1-sja1000' to handle these differences. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Hi Biju, On Sun, Jul 10, 2022 at 1:53 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add CAN binding documentation for Renesas RZ/N1 SoC. > > The SJA1000 CAN controller on RZ/N1 SoC has some differences compared > to others like it has no clock divider register (CDR) support and it has > no HW loopback (HW doesn't see tx messages on rx), so introduced a new > compatible 'renesas,rzn1-sja1000' to handle these differences. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Thanks for your patch, which is now commit 4591c760b7975984 ("dt-bindings: can: nxp,sja1000: Document RZ/N1{D,S} in v6.0-rc1. > --- a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml > +++ b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml > @@ -11,9 +11,15 @@ maintainers: > > properties: > compatible: > - enum: > - - nxp,sja1000 > - - technologic,sja1000 > + oneOf: > + - enum: > + - nxp,sja1000 > + - technologic,sja1000 > + - items: > + - enum: > + - renesas,r9a06g032-sja1000 # RZ/N1D > + - renesas,r9a06g033-sja1000 # RZ/N1S > + - const: renesas,rzn1-sja1000 # RZ/N1 > > reg: > maxItems: 1 > @@ -21,6 +27,9 @@ properties: > interrupts: > maxItems: 1 > > + clocks: > + maxItems: 1 > + Probably you want to add the power-domains property, and make it required on RZ/N1. This is not super-critical, as your driver patch uses explicit clock handling anyway. > reg-io-width: > $ref: /schemas/types.yaml#/definitions/uint32 > description: I/O register width (in bytes) implemented by this device Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH v4 2/6] dt-bindings: can: nxp,sja1000: Document > RZ/N1{D,S} support > > Hi Biju, > > On Sun, Jul 10, 2022 at 1:53 PM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > Add CAN binding documentation for Renesas RZ/N1 SoC. > > > > The SJA1000 CAN controller on RZ/N1 SoC has some differences compared > > to others like it has no clock divider register (CDR) support and it > > has no HW loopback (HW doesn't see tx messages on rx), so introduced a > > new compatible 'renesas,rzn1-sja1000' to handle these differences. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Thanks for your patch, which is now commit 4591c760b7975984 > ("dt-bindings: can: nxp,sja1000: Document RZ/N1{D,S} in v6.0-rc1. > > > --- a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml > > +++ b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml > > @@ -11,9 +11,15 @@ maintainers: > > > > properties: > > compatible: > > - enum: > > - - nxp,sja1000 > > - - technologic,sja1000 > > + oneOf: > > + - enum: > > + - nxp,sja1000 > > + - technologic,sja1000 > > + - items: > > + - enum: > > + - renesas,r9a06g032-sja1000 # RZ/N1D > > + - renesas,r9a06g033-sja1000 # RZ/N1S > > + - const: renesas,rzn1-sja1000 # RZ/N1 > > > > reg: > > maxItems: 1 > > @@ -21,6 +27,9 @@ properties: > > interrupts: > > maxItems: 1 > > > > + clocks: > > + maxItems: 1 > > + > > Probably you want to add the power-domains property, and make it > required on RZ/N1. > This is not super-critical, as your driver patch uses explicit clock > handling anyway. OK, will add this and Send SoC/Board dtsi patches. Cheers, Biju. > > > reg-io-width: > > $ref: /schemas/types.yaml#/definitions/uint32 > > description: I/O register width (in bytes) implemented by this > > device > > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But when I'm talking to journalists I just say "programmer" or something > like that. > -- Linus Torvalds
diff --git a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml index ca9bfdfa50ab..b1327c5b86cf 100644 --- a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml +++ b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml @@ -11,9 +11,15 @@ maintainers: properties: compatible: - enum: - - nxp,sja1000 - - technologic,sja1000 + oneOf: + - enum: + - nxp,sja1000 + - technologic,sja1000 + - items: + - enum: + - renesas,r9a06g032-sja1000 # RZ/N1D + - renesas,r9a06g033-sja1000 # RZ/N1S + - const: renesas,rzn1-sja1000 # RZ/N1 reg: maxItems: 1 @@ -21,6 +27,9 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 1 + reg-io-width: $ref: /schemas/types.yaml#/definitions/uint32 description: I/O register width (in bytes) implemented by this device @@ -82,10 +91,20 @@ allOf: properties: compatible: contains: - const: technologic,sja1000 + enum: + - technologic,sja1000 + - renesas,rzn1-sja1000 then: required: - reg-io-width + - if: + properties: + compatible: + contains: + const: renesas,rzn1-sja1000 + then: + required: + - clocks unevaluatedProperties: false @@ -99,3 +118,15 @@ examples: nxp,tx-output-config = <0x06>; nxp,external-clock-frequency = <24000000>; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + + can@52104000 { + compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; + reg = <0x52104000 0x800>; + reg-io-width = <4>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_CAN0>; + };
Add CAN binding documentation for Renesas RZ/N1 SoC. The SJA1000 CAN controller on RZ/N1 SoC has some differences compared to others like it has no clock divider register (CDR) support and it has no HW loopback (HW doesn't see tx messages on rx), so introduced a new compatible 'renesas,rzn1-sja1000' to handle these differences. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v3->v4: * Removed clock-names * Fixed indentation and added extra space in example. v2->v3: * Added reg-io-width is required property for renesas,rzn1-sja1000. v1->v2: * Updated commit description. * Added an example for RZ/N1D SJA1000 usage --- .../bindings/net/can/nxp,sja1000.yaml | 39 +++++++++++++++++-- 1 file changed, 35 insertions(+), 4 deletions(-)