| Message ID | 20220718195651.7711-5-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 086cd0ccfcbaa50060522fa4d1f19176a1f1695f |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add IRQC support to Renesas RZ/G2L and RZ/V2L SoC | expand |
On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add required properties in pinctrl node to handle GPIO interrupts. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.21. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 4b8a09abfc7f..24611e4a7913 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -644,6 +644,10 @@ pinctrl: pinctrl@11030000 { reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-parent = <&irqc>; + interrupt-controller; gpio-ranges = <&pinctrl 0 0 392>; clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; power-domains = <&cpg>;
Add required properties in pinctrl node to handle GPIO interrupts. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 4 ++++ 1 file changed, 4 insertions(+)