| Message ID | 20220726210110.1444-3-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 7adc69f8ac35109eab2742e6bb7a747dd811d1f6 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | r8a779f0: enable TMU | expand |
Hi Wolfram, On Tue, Jul 26, 2022 at 11:03 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi > @@ -334,6 +334,71 @@ tsc: thermal@e6198000 { > #thermal-sensor-cells = <1>; > }; > > + tmu0: timer@e61e0000 { > + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; > + reg = <0 0xe61e0000 0 0x30>; > + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 713>; > + clock-names = "fck"; > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > + resets = <&cpg 713>; > + status = "disabled"; > + }; > + > + tmu1: timer@e6fc0000 { > + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; > + reg = <0 0xe6fc0000 0 0x30>; > + interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; We really should update the DT bindings so we can describe the fourth interrupt on TMU instances that support input capture. I don't think we need a new compatible value, as we can just look at the presence of the fourth (actually renesas-channels + 1) interrupt to enable the feature (if the driver ever gains support). > + clocks = <&cpg CPG_MOD 714>; > + clock-names = "fck"; > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; > + resets = <&cpg 714>; > + status = "disabled"; > + }; As the above matches how TMU is handled on other SoCs: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.1. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, > > + interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; > > We really should update the DT bindings so we can describe the fourth > interrupt on TMU instances that support input capture. Yes, but I also think this should be a separate series then. > I don't think we need a new compatible value, as we can just look at > the presence of the fourth (actually renesas-channels + 1) interrupt > to enable the feature (if the driver ever gains support). Good approach. But then, we should also switch to interrupt names to be future proof, or? Who knows what other interrupts might be added later. > As the above matches how TMU is handled on other SoCs: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will queue in renesas-devel for v6.1. Thanks! Happy hacking, Wolfram
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 0c59a93cbaaa..61bd168f51c6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -334,6 +334,71 @@ tsc: thermal@e6198000 { #thermal-sensor-cells = <1>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 713>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c";
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 65 +++++++++++++++++++++++ 1 file changed, 65 insertions(+)