| Message ID | 20220801214718.16943-3-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Kieran Bingham |
| Headers | show |
| Series | Add driver for CSI2 and CRU modules found on Renesas RZ/G2L SoC | expand |
On 01/08/2022 23:47, Lad Prabhakar wrote: > Document the CRU block found on Renesas RZ/G2L SoC's. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > RFC v2 -> v1 > * Dropped endpoint stuff from port1 as suggested by Rob > * Updated description for endpoint > > RFC v1 -> RFC v2 > * Dropped CSI > --- > .../bindings/media/renesas,rzg2l-cru.yaml | 142 ++++++++++++++++++ > 1 file changed, 142 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > > diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > new file mode 100644 > index 000000000000..d7389693dae9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > @@ -0,0 +1,142 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (C) 2022 Renesas Electronics Corp. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing > + > +maintainers: > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > + > +description: > + The CRU image processing module is a data conversion module equipped with pixel > + color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and > + parallel (including ITU-R BT.656) input are provided as the image sensor interface. > + > +properties: > + compatible: > + oneOf: No need for oneOf, unless you already have a patch adding second case to oneOf. > + - items: > + - enum: > + - renesas,r9a07g044-cru # RZ/G2{L,LC} > + - renesas,r9a07g054-cru # RZ/V2L > + - const: renesas,rzg2l-cru > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 3 > + > + interrupt-names: > + items: > + - const: image_conv > + - const: image_conv_err > + - const: axi_mst_err > + > + clocks: > + items: > + - description: CRU Main clock > + - description: CPU Register access clock > + - description: CRU image transfer clock > + > + clock-names: > + items: > + - const: vclk > + - const: pclk > + - const: aclk > + > + power-domains: > + maxItems: 1 > + > + resets: > + items: > + - description: CRU_PRESETN reset terminal > + - description: CRU_ARESETN reset terminal > + > + reset-names: > + items: > + - const: presetn > + - const: aresetn > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port node, single endpoint describing a parallel input source. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + hsync-active: true > + vsync-active: true > + bus-width: true > + data-shift: true > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Input port node, describing the Image Processing module connected to the > + CSI-2 receiver. > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + - clock-names > + - resets > + - reset-names > + - power-domains > + > +additionalProperties: false > + > +examples: > + # Device node example with CSI-2 > + - | > + #include <dt-bindings/clock/r9a07g044-cpg.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + cru: video@10830000 { > + compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; Also 4-space for DTS example, please. Best regards, Krzysztof
Hi Krzysztof, Thank you for the review. On Tue, Aug 2, 2022 at 8:37 AM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 01/08/2022 23:47, Lad Prabhakar wrote: > > Document the CRU block found on Renesas RZ/G2L SoC's. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > RFC v2 -> v1 > > * Dropped endpoint stuff from port1 as suggested by Rob > > * Updated description for endpoint > > > > RFC v1 -> RFC v2 > > * Dropped CSI > > --- > > .../bindings/media/renesas,rzg2l-cru.yaml | 142 ++++++++++++++++++ > > 1 file changed, 142 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > > new file mode 100644 > > index 000000000000..d7389693dae9 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > > @@ -0,0 +1,142 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (C) 2022 Renesas Electronics Corp. > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing > > + > > +maintainers: > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > + > > +description: > > + The CRU image processing module is a data conversion module equipped with pixel > > + color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and > > + parallel (including ITU-R BT.656) input are provided as the image sensor interface. > > + > > +properties: > > + compatible: > > + oneOf: > > No need for oneOf, unless you already have a patch adding second case to > oneOf. > Agreed, I will drop that. > > + - items: > > + - enum: > > + - renesas,r9a07g044-cru # RZ/G2{L,LC} > > + - renesas,r9a07g054-cru # RZ/V2L > > + - const: renesas,rzg2l-cru > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 3 > > + > > + interrupt-names: > > + items: > > + - const: image_conv > > + - const: image_conv_err > > + - const: axi_mst_err > > + > > + clocks: > > + items: > > + - description: CRU Main clock > > + - description: CPU Register access clock > > + - description: CRU image transfer clock > > + > > + clock-names: > > + items: > > + - const: vclk > > + - const: pclk > > + - const: aclk > > + > > + power-domains: > > + maxItems: 1 > > + > > + resets: > > + items: > > + - description: CRU_PRESETN reset terminal > > + - description: CRU_ARESETN reset terminal > > + > > + reset-names: > > + items: > > + - const: presetn > > + - const: aresetn > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/$defs/port-base > > + unevaluatedProperties: false > > + description: > > + Input port node, single endpoint describing a parallel input source. > > + > > + properties: > > + endpoint: > > + $ref: video-interfaces.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + hsync-active: true > > + vsync-active: true > > + bus-width: true > > + data-shift: true > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Input port node, describing the Image Processing module connected to the > > + CSI-2 receiver. > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - interrupt-names > > + - clocks > > + - clock-names > > + - resets > > + - reset-names > > + - power-domains > > + > > +additionalProperties: false > > + > > +examples: > > + # Device node example with CSI-2 > > + - | > > + #include <dt-bindings/clock/r9a07g044-cpg.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > + cru: video@10830000 { > > + compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; > > Also 4-space for DTS example, please. > Agreed. Cheers, Prabhakar
Hi Prabhakar, Thank you for the patch. On Mon, Aug 01, 2022 at 10:47:16PM +0100, Lad Prabhakar wrote: > Document the CRU block found on Renesas RZ/G2L SoC's. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > RFC v2 -> v1 > * Dropped endpoint stuff from port1 as suggested by Rob > * Updated description for endpoint > > RFC v1 -> RFC v2 > * Dropped CSI > --- > .../bindings/media/renesas,rzg2l-cru.yaml | 142 ++++++++++++++++++ > 1 file changed, 142 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > > diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > new file mode 100644 > index 000000000000..d7389693dae9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > @@ -0,0 +1,142 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (C) 2022 Renesas Electronics Corp. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing > + > +maintainers: > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > + > +description: > + The CRU image processing module is a data conversion module equipped with pixel > + color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and > + parallel (including ITU-R BT.656) input are provided as the image sensor interface. > + > +properties: > + compatible: > + oneOf: No oneOf here either. > + - items: > + - enum: > + - renesas,r9a07g044-cru # RZ/G2{L,LC} > + - renesas,r9a07g054-cru # RZ/V2L > + - const: renesas,rzg2l-cru > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 3 > + > + interrupt-names: > + items: > + - const: image_conv > + - const: image_conv_err > + - const: axi_mst_err > + > + clocks: > + items: > + - description: CRU Main clock > + - description: CPU Register access clock > + - description: CRU image transfer clock > + > + clock-names: > + items: > + - const: vclk > + - const: pclk > + - const: aclk > + > + power-domains: > + maxItems: 1 > + > + resets: > + items: > + - description: CRU_PRESETN reset terminal > + - description: CRU_ARESETN reset terminal > + > + reset-names: > + items: > + - const: presetn > + - const: aresetn > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port node, single endpoint describing a parallel input source. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + hsync-active: true > + vsync-active: true > + bus-width: true > + data-shift: true > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Input port node, describing the Image Processing module connected to the > + CSI-2 receiver. Both ports should be mandatory as they exist at the hardware level. Connections (through endpoints) are optional. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + - clock-names > + - resets > + - reset-names > + - power-domains > + > +additionalProperties: false > + > +examples: > + # Device node example with CSI-2 > + - | > + #include <dt-bindings/clock/r9a07g044-cpg.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + cru: video@10830000 { > + compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; > + reg = <0x10830000 0x400>; > + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; > + clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>, > + <&cpg CPG_MOD R9A07G044_CRU_PCLK>, > + <&cpg CPG_MOD R9A07G044_CRU_ACLK>; > + clock-names = "vclk", "pclk", "aclk"; > + power-domains = <&cpg>; > + resets = <&cpg R9A07G044_CRU_PRESETN>, > + <&cpg R9A07G044_CRU_ARESETN>; > + reset-names = "presetn", "aresetn"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg = <1>; > + > + crucsi2: endpoint@0 { > + reg = <0>; > + remote-endpoint= <&csi2cru>; > + }; > + }; > + }; > + };
Hi Laurent, Thank you for the review. On Tue, Aug 30, 2022 at 12:42 AM Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > > Hi Prabhakar, > > Thank you for the patch. > > On Mon, Aug 01, 2022 at 10:47:16PM +0100, Lad Prabhakar wrote: > > Document the CRU block found on Renesas RZ/G2L SoC's. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > RFC v2 -> v1 > > * Dropped endpoint stuff from port1 as suggested by Rob > > * Updated description for endpoint > > > > RFC v1 -> RFC v2 > > * Dropped CSI > > --- > > .../bindings/media/renesas,rzg2l-cru.yaml | 142 ++++++++++++++++++ > > 1 file changed, 142 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > > new file mode 100644 > > index 000000000000..d7389693dae9 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml > > @@ -0,0 +1,142 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (C) 2022 Renesas Electronics Corp. > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing > > + > > +maintainers: > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > + > > +description: > > + The CRU image processing module is a data conversion module equipped with pixel > > + color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and > > + parallel (including ITU-R BT.656) input are provided as the image sensor interface. > > + > > +properties: > > + compatible: > > + oneOf: > > No oneOf here either. > Agreed, I will drop it. > > + - items: > > + - enum: > > + - renesas,r9a07g044-cru # RZ/G2{L,LC} > > + - renesas,r9a07g054-cru # RZ/V2L > > + - const: renesas,rzg2l-cru > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 3 > > + > > + interrupt-names: > > + items: > > + - const: image_conv > > + - const: image_conv_err > > + - const: axi_mst_err > > + > > + clocks: > > + items: > > + - description: CRU Main clock > > + - description: CPU Register access clock > > + - description: CRU image transfer clock > > + > > + clock-names: > > + items: > > + - const: vclk > > + - const: pclk > > + - const: aclk > > + > > + power-domains: > > + maxItems: 1 > > + > > + resets: > > + items: > > + - description: CRU_PRESETN reset terminal > > + - description: CRU_ARESETN reset terminal > > + > > + reset-names: > > + items: > > + - const: presetn > > + - const: aresetn > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/$defs/port-base > > + unevaluatedProperties: false > > + description: > > + Input port node, single endpoint describing a parallel input source. > > + > > + properties: > > + endpoint: > > + $ref: video-interfaces.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + hsync-active: true > > + vsync-active: true > > + bus-width: true > > + data-shift: true > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: > > + Input port node, describing the Image Processing module connected to the > > + CSI-2 receiver. > > Both ports should be mandatory as they exist at the hardware level. > Connections (through endpoints) are optional. > Agreed, I will make the ports as required. Cheers, Prabhakar
diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml new file mode 100644 index 000000000000..d7389693dae9 --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + The CRU image processing module is a data conversion module equipped with pixel + color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and + parallel (including ITU-R BT.656) input are provided as the image sensor interface. + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r9a07g044-cru # RZ/G2{L,LC} + - renesas,r9a07g054-cru # RZ/V2L + - const: renesas,rzg2l-cru + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: image_conv + - const: image_conv_err + - const: axi_mst_err + + clocks: + items: + - description: CRU Main clock + - description: CPU Register access clock + - description: CRU image transfer clock + + clock-names: + items: + - const: vclk + - const: pclk + - const: aclk + + power-domains: + maxItems: 1 + + resets: + items: + - description: CRU_PRESETN reset terminal + - description: CRU_ARESETN reset terminal + + reset-names: + items: + - const: presetn + - const: aresetn + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port node, single endpoint describing a parallel input source. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + hsync-active: true + vsync-active: true + bus-width: true + data-shift: true + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Input port node, describing the Image Processing module connected to the + CSI-2 receiver. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + +additionalProperties: false + +examples: + # Device node example with CSI-2 + - | + #include <dt-bindings/clock/r9a07g044-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + cru: video@10830000 { + compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; + reg = <0x10830000 0x400>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>, + <&cpg CPG_MOD R9A07G044_CRU_PCLK>, + <&cpg CPG_MOD R9A07G044_CRU_ACLK>; + clock-names = "vclk", "pclk", "aclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_CRU_PRESETN>, + <&cpg R9A07G044_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi2cru>; + }; + }; + }; + };
Document the CRU block found on Renesas RZ/G2L SoC's. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- RFC v2 -> v1 * Dropped endpoint stuff from port1 as suggested by Rob * Updated description for endpoint RFC v1 -> RFC v2 * Dropped CSI --- .../bindings/media/renesas,rzg2l-cru.yaml | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml