| Message ID | 20220802101534.1401342-3-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 72a482dbaec4b9e4d54b81be6bdb8c016fd2f4bd |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [1/3] arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt type | expand |
On Tue, Aug 2, 2022 at 12:15 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022), > the interrupt type of SCI{Rx,TX} is edge triggered. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC") Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.1. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index d1b567d1b6e1..ff6aab388eb7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -340,8 +340,8 @@ sci0: serial@1004d000 { compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d000 0 0x400>; interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; @@ -355,8 +355,8 @@ sci1: serial@1004d400 { compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d400 0 0x400>; interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022), the interrupt type of SCI{Rx,TX} is edge triggered. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)