Message ID | 20220815151451.23293-3-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
---|---|
State | Mainlined |
Commit | 9f643dc28e2c072d7d323898530ee37433e74595 |
Delegated to: | Geert Uytterhoeven |
Headers | show |
Series | Add support for Renesas RZ/Five SoC | expand |
On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > Single) from Andes. In preparation to add support for RZ/Five SoC add > the Andes AX45MP core to the list. > > More details about Andes AX45MP core can be found here: > [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 2a1c5ae5b0aa..1681767790c5 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -27,6 +27,7 @@ properties: oneOf: - items: - enum: + - andestech,ax45mp - canaan,k210 - sifive,bullet0 - sifive,e5