| Message ID | 20220815151451.23293-4-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add support for Renesas RZ/Five SoC | expand |
On 15/08/2022 16:14, Lad Prabhakar wrote: > dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Hey Lad, Maybe I am missing something on the arm side, but "soc"? Was the intent to move this to Documentation/devicetree/bindings/soc but you moved it back to arm by accident? Thanks, Conor. > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Document Renesas RZ/Five (R9A07G043) SoC. > > More info about RZ/Five SoC: > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v1->v2 > * New patch > --- > Documentation/devicetree/bindings/arm/renesas.yaml | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml > index ff80152f092f..233847eb23fd 100644 > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > @@ -415,11 +415,12 @@ properties: > - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) > - const: renesas,r9a06g032 > > - - description: RZ/G2UL (R9A07G043) > + - description: RZ/Five and RZ/G2UL (R9A07G043) > items: > - enum: > - renesas,smarc-evk # SMARC EVK > - enum: > + - renesas,r9a07g043f01 # RZ/Five (RISC-V core) > - renesas,r9a07g043u11 # RZ/G2UL Type-1 > - renesas,r9a07g043u12 # RZ/G2UL Type-2 > - const: renesas,r9a07g043 > -- > 2.25.1 >
Hi Conor, Thank you for the review. On Mon, Aug 15, 2022 at 8:14 PM <Conor.Dooley@microchip.com> wrote: > > On 15/08/2022 16:14, Lad Prabhakar wrote: > > dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC > > Hey Lad, > > Maybe I am missing something on the arm side, but "soc"? > Was the intent to move this to Documentation/devicetree/bindings/soc > but you moved it back to arm by accident? > Ouch I sent out the older version of my patch for this. I did actually send out a patch which moves arm renesas.yaml to the soc folder. Cheers, Prabhakar > Thanks, > Conor. > > > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Document Renesas RZ/Five (R9A07G043) SoC. > > > > More info about RZ/Five SoC: > > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v1->v2 > > * New patch > > --- > > Documentation/devicetree/bindings/arm/renesas.yaml | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml > > index ff80152f092f..233847eb23fd 100644 > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > > @@ -415,11 +415,12 @@ properties: > > - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) > > - const: renesas,r9a06g032 > > > > - - description: RZ/G2UL (R9A07G043) > > + - description: RZ/Five and RZ/G2UL (R9A07G043) > > items: > > - enum: > > - renesas,smarc-evk # SMARC EVK > > - enum: > > + - renesas,r9a07g043f01 # RZ/Five (RISC-V core) > > - renesas,r9a07g043u11 # RZ/G2UL Type-1 > > - renesas,r9a07g043u12 # RZ/G2UL Type-2 > > - const: renesas,r9a07g043 > > -- > > 2.25.1 > > >
On 15/08/2022 20:40, Lad, Prabhakar wrote: > Hi Conor, > > Thank you for the review. > > On Mon, Aug 15, 2022 at 8:14 PM <Conor.Dooley@microchip.com> wrote: >> >> On 15/08/2022 16:14, Lad Prabhakar wrote: >>> dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC >> >> Hey Lad, >> >> Maybe I am missing something on the arm side, but "soc"? >> Was the intent to move this to Documentation/devicetree/bindings/soc >> but you moved it back to arm by accident? >> > Ouch I sent out the older version of my patch for this. I did actually > send out a patch which moves arm renesas.yaml to the soc folder. Cool thought I saw one of those this morning. > > Cheers, > Prabhakar > >> Thanks, >> Conor. >> >> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> Document Renesas RZ/Five (R9A07G043) SoC. >>> >>> More info about RZ/Five SoC: >>> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet >>> >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> >>> --- >>> v1->v2 >>> * New patch >>> --- >>> Documentation/devicetree/bindings/arm/renesas.yaml | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml >>> index ff80152f092f..233847eb23fd 100644 >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml >>> @@ -415,11 +415,12 @@ properties: >>> - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) >>> - const: renesas,r9a06g032 >>> >>> - - description: RZ/G2UL (R9A07G043) >>> + - description: RZ/Five and RZ/G2UL (R9A07G043) >>> items: >>> - enum: >>> - renesas,smarc-evk # SMARC EVK >>> - enum: >>> + - renesas,r9a07g043f01 # RZ/Five (RISC-V core) >>> - renesas,r9a07g043u11 # RZ/G2UL Type-1 >>> - renesas,r9a07g043u12 # RZ/G2UL Type-2 >>> - const: renesas,r9a07g043 >>> -- >>> 2.25.1 >>> >> > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 15/08/2022 18:14, Lad Prabhakar wrote: > Document Renesas RZ/Five (R9A07G043) SoC. > > More info about RZ/Five SoC: > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Hi Prabhakar, On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Document Renesas RZ/Five (R9A07G043) SoC. > > More info about RZ/Five SoC: > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > @@ -415,11 +415,12 @@ properties: > - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) > - const: renesas,r9a06g032 > > - - description: RZ/G2UL (R9A07G043) > + - description: RZ/Five and RZ/G2UL (R9A07G043) > items: > - enum: > - renesas,smarc-evk # SMARC EVK > - enum: > + - renesas,r9a07g043f01 # RZ/Five (RISC-V core) Should we be consistent, and leave out the "(RISC-V core)" comment, or add it everywhere? Note that several of the SoCs listed in this file have SuperH or RealTime ARM cores, so going for the former means a lot of work. > - renesas,r9a07g043u11 # RZ/G2UL Type-1 > - renesas,r9a07g043u12 # RZ/G2UL Type-2 > - const: renesas,r9a07g043 Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thank you for the review. On Thu, Aug 18, 2022 at 4:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Aug 15, 2022 at 5:16 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Document Renesas RZ/Five (R9A07G043) SoC. > > > > More info about RZ/Five SoC: > > https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml > > @@ -415,11 +415,12 @@ properties: > > - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) > > - const: renesas,r9a06g032 > > > > - - description: RZ/G2UL (R9A07G043) > > + - description: RZ/Five and RZ/G2UL (R9A07G043) > > items: > > - enum: > > - renesas,smarc-evk # SMARC EVK > > - enum: > > + - renesas,r9a07g043f01 # RZ/Five (RISC-V core) > > Should we be consistent, and leave out the "(RISC-V core)" comment, > or add it everywhere? > Rather leave it for now ;) . If Rob agrees on your suggestion on splitting (renesas,{rmobile,rcar-gen[1234],rza,rzg,rzn,...}.yaml that would make it cleaner. > Note that several of the SoCs listed in this file have SuperH or > RealTime ARM cores, so going for the former means a lot of work. > Agreed. Cheers, Prabhakar
diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index ff80152f092f..233847eb23fd 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -415,11 +415,12 @@ properties: - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) - const: renesas,r9a06g032 - - description: RZ/G2UL (R9A07G043) + - description: RZ/Five and RZ/G2UL (R9A07G043) items: - enum: - renesas,smarc-evk # SMARC EVK - enum: + - renesas,r9a07g043f01 # RZ/Five (RISC-V core) - renesas,r9a07g043u11 # RZ/G2UL Type-1 - renesas,r9a07g043u12 # RZ/G2UL Type-2 - const: renesas,r9a07g043
Document Renesas RZ/Five (R9A07G043) SoC. More info about RZ/Five SoC: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- v1->v2 * New patch --- Documentation/devicetree/bindings/arm/renesas.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)