diff mbox series

[v4] ARM: dts: r9a06g032-rzn1d400-db: Enable CAN2

Message ID 20220901162919.47090-1-biju.das.jz@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series [v4] ARM: dts: r9a06g032-rzn1d400-db: Enable CAN2 | expand

Commit Message

Biju Das Sept. 1, 2022, 4:29 p.m. UTC
Enable CAN2 on RZ/N1-EB board by default.
Also add a macro to enable CAN1, if the board
support it.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3->v4:
 * Updated commit descriptiom
 * Enabled CAN2 by default
 * Added a macro BOARD_HAS_CAN1_ENABLED to configure CAN1,
   if the board supports it.
v2->v3:
 * No change
v1->v2:
 * No change
---
 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 28 +++++++++++++++++++++
 1 file changed, 28 insertions(+)

Comments

Geert Uytterhoeven Sept. 1, 2022, 5:10 p.m. UTC | #1
Hi Biju,

On Thu, Sep 1, 2022 at 6:29 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Enable CAN2 on RZ/N1-EB board by default.
> Also add a macro to enable CAN1, if the board
> support it.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v3->v4:
>  * Updated commit descriptiom
>  * Enabled CAN2 by default
>  * Added a macro BOARD_HAS_CAN1_ENABLED to configure CAN1,
>    if the board supports it.

Thanks for the update!

> --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
> +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
> @@ -26,6 +26,22 @@ aliases {
>         };
>  };
>
> +#if BOARD_HAS_CAN1_ENABLED /* CN10 on RZ/N1-EB board */
> +&can0 {
> +       pinctrl-0 = <&pins_can0>;
> +       pinctrl-names = "default";
> +
> +       status = "okay";
> +};
> +#endif
> +
> +&can1 {
> +       pinctrl-0 = <&pins_can1>;
> +       pinctrl-names = "default";
> +
> +       status = "okay";
> +};

AFAIU, CN10 and CN11 are not the real CAN connectors, they are headers
to add jumpers to select which CAN interface to route to the real CAN
connector J16.

Hence I was thinking of something along the line:

    #ifdef BOARD_HAS_CAN1_ENABLED
    &can0 {
           pinctrl-0 = <&pins_can0>;
           pinctrl-names = "default";

           status = "okay";
    };
    #else
    &can1 {
           pinctrl-0 = <&pins_can1>;
           pinctrl-names = "default";

           status = "okay";
    };
    #endif

or:

   &can0 {
           pinctrl-0 = <&pins_can0>;
           pinctrl-names = "default";

           /* Assuming CN10/CN11 are wired for CAN1 */
           status = "okay";
    };

    &can1 {
           pinctrl-0 = <&pins_can1>;
           pinctrl-names = "default";

           /* Please only enable can0 or can1, depending on CN10/CN11 */
           /* status = "okay"; */
    };


Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Biju Das Sept. 1, 2022, 5:56 p.m. UTC | #2
Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v4] ARM: dts: r9a06g032-rzn1d400-db: Enable CAN2
> 
> Hi Biju,
> 
> On Thu, Sep 1, 2022 at 6:29 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Enable CAN2 on RZ/N1-EB board by default.
> > Also add a macro to enable CAN1, if the board support it.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v3->v4:
> >  * Updated commit descriptiom
> >  * Enabled CAN2 by default
> >  * Added a macro BOARD_HAS_CAN1_ENABLED to configure CAN1,
> >    if the board supports it.
> 
> Thanks for the update!
> 
> > --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
> > +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
> > @@ -26,6 +26,22 @@ aliases {
> >         };
> >  };
> >
> > +#if BOARD_HAS_CAN1_ENABLED /* CN10 on RZ/N1-EB board */
> > +&can0 {
> > +       pinctrl-0 = <&pins_can0>;
> > +       pinctrl-names = "default";
> > +
> > +       status = "okay";
> > +};
> > +#endif
> > +
> > +&can1 {
> > +       pinctrl-0 = <&pins_can1>;
> > +       pinctrl-names = "default";
> > +
> > +       status = "okay";
> > +};
> 
> AFAIU, CN10 and CN11 are not the real CAN connectors, they are headers
> to add jumpers to select which CAN interface to route to the real CAN
> connector J16.
> 
> Hence I was thinking of something along the line:
> 
>     #ifdef BOARD_HAS_CAN1_ENABLED
>     &can0 {
>            pinctrl-0 = <&pins_can0>;
>            pinctrl-names = "default";
> 
>            status = "okay";
>     };
>     #else
>     &can1 {
>            pinctrl-0 = <&pins_can1>;
>            pinctrl-names = "default";
> 
>            status = "okay";
>     };
>     #endif
> 
> or:
> 
>    &can0 {
>            pinctrl-0 = <&pins_can0>;
>            pinctrl-names = "default";
> 
>            /* Assuming CN10/CN11 are wired for CAN1 */
>            status = "okay";
>     };
> 
>     &can1 {
>            pinctrl-0 = <&pins_can1>;
>            pinctrl-names = "default";
> 
>            /* Please only enable can0 or can1, depending on CN10/CN11 */
>            /* status = "okay"; */
>     };

OK, will use the later one, to make BSP testing easier.

Cheers,
Biju
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
index 4bf813335e21..c073ca360866 100644
--- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -26,6 +26,22 @@  aliases {
 	};
 };
 
+#if BOARD_HAS_CAN1_ENABLED /* CN10 on RZ/N1-EB board */
+&can0 {
+	pinctrl-0 = <&pins_can0>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+#endif
+
+&can1 {
+	pinctrl-0 = <&pins_can1>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
 &eth_miic {
 	status = "okay";
 	renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
@@ -52,6 +68,18 @@  &mii_conv5 {
 };
 
 &pinctrl{
+	pins_can0: pins_can0 {
+		pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>,	/* CAN0_TXD */
+			 <RZN1_PINMUX(163, RZN1_FUNC_CAN)>;	/* CAN0_RXD */
+		drive-strength = <6>;
+	};
+
+	pins_can1: pins_can1 {
+		pinmux = <RZN1_PINMUX(109, RZN1_FUNC_CAN)>,	/* CAN1_TXD */
+			 <RZN1_PINMUX(110, RZN1_FUNC_CAN)>;	/* CAN1_RXD */
+		drive-strength = <6>;
+	};
+
 	pins_eth3: pins_eth3 {
 		pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
 			 <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,