| Message ID | 20220915181558.354737-8-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add support for Renesas RZ/Five SoC | expand |
On 15/09/2022 19:15, Prabhakar wrote: > riscv: boot: dts: r9a07g043: Add placeholder nodes nit: s/boot// > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI. Can you explain why do you need placeholder nodes for this and cannot just directly include the other dtsis? > > This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier > board DTS/I. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v1->v3 > * New patch > --- > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 177 +++++++++++++++++++++ > 1 file changed, 177 insertions(+) > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > index fb6733f3cc2b..6d9db759a847 100644 > --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > @@ -13,6 +13,14 @@ / { > #address-cells = <2>; > #size-cells = <2>; > > + audio_clk1: audio1-clk { > + /* placeholder */ > + }; > + > + audio_clk2: audio2-clk { > + /* placeholder */ > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -54,6 +62,23 @@ soc: soc { > #size-cells = <2>; > ranges; > > + ssi1: ssi@1004a000 { > + reg = <0 0x1004a000 0 0x400>; > + #sound-dai-cells = <0>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + spi1: spi@1004b000 { > + reg = <0 0x1004b000 0 0x400>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > scif0: serial@1004b800 { > compatible = "renesas,scif-r9a07g043", > "renesas,scif-r9a07g044"; > @@ -73,6 +98,48 @@ scif0: serial@1004b800 { > status = "disabled"; > }; > > + canfd: can@10050000 { > + reg = <0 0x10050000 0 0x8000>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + i2c0: i2c@10058000 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0 0x10058000 0 0x400>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + i2c1: i2c@10058400 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0 0x10058400 0 0x400>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + adc: adc@10059000 { > + reg = <0 0x10059000 0 0x400>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + sbc: spi@10060000 { > + reg = <0 0x10060000 0 0x10000>, > + <0 0x20000000 0 0x10000000>, > + <0 0x10070000 0 0x10000>; > + reg-names = "regs", "dirmap", "wbuf"; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > cpg: clock-controller@11010000 { > compatible = "renesas,r9a07g043-cpg"; > reg = <0 0x11010000 0 0x10000>; > @@ -104,6 +171,95 @@ pinctrl: pinctrl@11030000 { > <&cpg R9A07G043_GPIO_SPARE_RESETN>; > }; > > + sdhi0: mmc@11c00000 { > + reg = <0x0 0x11c00000 0 0x10000>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + sdhi1: mmc@11c10000 { > + reg = <0x0 0x11c10000 0 0x10000>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + eth0: ethernet@11c20000 { > + reg = <0 0x11c20000 0 0x10000>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + eth1: ethernet@11c30000 { > + reg = <0 0x11c30000 0 0x10000>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + phyrst: usbphy-ctrl@11c40000 { > + reg = <0 0x11c40000 0 0x10000>; > + #reset-cells = <1>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + ohci0: usb@11c50000 { > + reg = <0 0x11c50000 0 0x100>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + ohci1: usb@11c70000 { > + reg = <0 0x11c70000 0 0x100>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + ehci0: usb@11c50100 { > + reg = <0 0x11c50100 0 0x100>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + ehci1: usb@11c70100 { > + reg = <0 0x11c70100 0 0x100>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + usb2_phy0: usb-phy@11c50200 { > + reg = <0 0x11c50200 0 0x700>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + usb2_phy1: usb-phy@11c70200 { > + reg = <0 0x11c70200 0 0x700>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + hsusb: usb@11c60000 { > + reg = <0 0x11c60000 0 0x10000>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > plic: interrupt-controller@12c00000 { > compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; > #interrupt-cells = <2>; > @@ -116,5 +272,26 @@ plic: interrupt-controller@12c00000 { > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; > }; > + > + wdt0: watchdog@12800800 { > + reg = <0 0x12800800 0 0x400>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + ostm1: timer@12801400 { > + reg = <0x0 0x12801400 0x0 0x400>; > + status = "disabled"; > + > + /* placeholder */ > + }; > + > + ostm2: timer@12801800 { > + reg = <0x0 0x12801800 0x0 0x400>; > + status = "disabled"; > + > + /* placeholder */ > + }; > }; > }; > -- > 2.25.1 >
Hi Conor, Thank you for the review. On Thu, Sep 15, 2022 at 10:36 PM <Conor.Dooley@microchip.com> wrote: > > On 15/09/2022 19:15, Prabhakar wrote: > > riscv: boot: dts: r9a07g043: Add placeholder nodes > > nit: s/boot// > Will fix that. > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI. > > Can you explain why do you need placeholder nodes for this and > cannot just directly include the other dtsis? > Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC we have PLIC for interrupts. Also the interrupt numbering for RZ/Five SoC differs from RZ/G2UL SoC hence we are not directly using the RZ/G2UL SoC DTSI [0]. [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5 For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since I am re-using these when trying to compile the RZ/Five DTB I get compilation errors since the nodes dont exist (and there is no way currently we can delete the node reference when the actual node itself isn't present) hence these place holders. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5 Cheers, Prabhakar
On 15/09/2022 23:26, Lad, Prabhakar wrote: > Hi Conor, > > Thank you for the review. > > On Thu, Sep 15, 2022 at 10:36 PM <Conor.Dooley@microchip.com> wrote: >> >> On 15/09/2022 19:15, Prabhakar wrote: >>> riscv: boot: dts: r9a07g043: Add placeholder nodes >> >> nit: s/boot// >> > Will fix that. > >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> >>> >>> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI. >> >> Can you explain why do you need placeholder nodes for this and >> cannot just directly include the other dtsis? >> > Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC > we have PLIC for interrupts. Also the interrupt numbering for RZ/Five > SoC differs from RZ/G2UL SoC hence we are not directly using the > RZ/G2UL SoC DTSI [0]. > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5 > > For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since > I am re-using these when trying to compile the RZ/Five DTB I get > compilation errors since the nodes dont exist (and there is no way > currently we can delete the node reference when the actual node itself > isn't present) hence these place holders. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5 If this method is acceptable to Geert, this explanation 100% needs to go into the commit message. Thanks, Conor.
Hi Conor, On Fri, Sep 16, 2022 at 12:40 AM Conor Dooley <mail@conchuod.ie> wrote: > On 15/09/2022 23:26, Lad, Prabhakar wrote: > > On Thu, Sep 15, 2022 at 10:36 PM <Conor.Dooley@microchip.com> wrote: > >> On 15/09/2022 19:15, Prabhakar wrote: > >>> riscv: boot: dts: r9a07g043: Add placeholder nodes > >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > >>> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI. > >> Can you explain why do you need placeholder nodes for this and > >> cannot just directly include the other dtsis? > >> > > Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC > > we have PLIC for interrupts. Also the interrupt numbering for RZ/Five > > SoC differs from RZ/G2UL SoC hence we are not directly using the > > RZ/G2UL SoC DTSI [0]. > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5 > > > > For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and > > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since > > I am re-using these when trying to compile the RZ/Five DTB I get > > compilation errors since the nodes dont exist (and there is no way > > currently we can delete the node reference when the actual node itself > > isn't present) hence these place holders. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5 > > If this method is acceptable to Geert, this explanation 100% needs to > go into the commit message. We've been using these placeholders a lot in Renesas SoC-specific .dtsi files, as they allow us to introduce gradually support for a new SoC that is mounted on an existing PCB, and thus shares a board-specific .dtsi file. Hence I'm fine with this. However, I think more properties can be dropped from the placeholders. There is no need to have e.g. 'reg-names' and 'status = "disabled"' (there is no compatible value, so no matching is done). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Tue, Sep 20, 2022 at 02:17:50PM +0200, Geert Uytterhoeven wrote: > Hi Conor, > > On Fri, Sep 16, 2022 at 12:40 AM Conor Dooley <mail@conchuod.ie> wrote: > > On 15/09/2022 23:26, Lad, Prabhakar wrote: > > > On Thu, Sep 15, 2022 at 10:36 PM <Conor.Dooley@microchip.com> wrote: > > >> On 15/09/2022 19:15, Prabhakar wrote: > > >>> riscv: boot: dts: r9a07g043: Add placeholder nodes > > >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > >>> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI. > > >> Can you explain why do you need placeholder nodes for this and > > >> cannot just directly include the other dtsis? > > >> > > > Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC > > > we have PLIC for interrupts. Also the interrupt numbering for RZ/Five > > > SoC differs from RZ/G2UL SoC hence we are not directly using the > > > RZ/G2UL SoC DTSI [0]. > > > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5 > > > > > > For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and > > > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since > > > I am re-using these when trying to compile the RZ/Five DTB I get > > > compilation errors since the nodes dont exist (and there is no way > > > currently we can delete the node reference when the actual node itself > > > isn't present) hence these place holders. > > > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5 > > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5 > > > > If this method is acceptable to Geert, this explanation 100% needs to > > go into the commit message. > > We've been using these placeholders a lot in Renesas SoC-specific > .dtsi files, as they allow us to introduce gradually support for a new SoC > that is mounted on an existing PCB, and thus shares a board-specific > .dtsi file. Hence I'm fine with this. Aye, if you're happy with it then I am too... > > However, I think more properties can be dropped from the placeholders. > There is no need to have e.g. 'reg-names' and 'status = "disabled"' > (there is no compatible value, so no matching is done). ...and this makes a lot of sense. I'd still like a comment in the commit message though explaining why placeholder nodes are needed as opposed to just leaving it blank etc. Thanks, Conor.
Hi Conor and Geert, On Tue, Sep 20, 2022 at 1:31 PM Conor Dooley <conor.dooley@microchip.com> wrote: > > On Tue, Sep 20, 2022 at 02:17:50PM +0200, Geert Uytterhoeven wrote: > > Hi Conor, > > > > On Fri, Sep 16, 2022 at 12:40 AM Conor Dooley <mail@conchuod.ie> wrote: > > > On 15/09/2022 23:26, Lad, Prabhakar wrote: > > > > On Thu, Sep 15, 2022 at 10:36 PM <Conor.Dooley@microchip.com> wrote: > > > >> On 15/09/2022 19:15, Prabhakar wrote: > > > >>> riscv: boot: dts: r9a07g043: Add placeholder nodes > > > >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > >>> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI. > > > >> Can you explain why do you need placeholder nodes for this and > > > >> cannot just directly include the other dtsis? > > > >> > > > > Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC > > > > we have PLIC for interrupts. Also the interrupt numbering for RZ/Five > > > > SoC differs from RZ/G2UL SoC hence we are not directly using the > > > > RZ/G2UL SoC DTSI [0]. > > > > > > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5 > > > > > > > > For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and > > > > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since > > > > I am re-using these when trying to compile the RZ/Five DTB I get > > > > compilation errors since the nodes dont exist (and there is no way > > > > currently we can delete the node reference when the actual node itself > > > > isn't present) hence these place holders. > > > > > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5 > > > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5 > > > > > > If this method is acceptable to Geert, this explanation 100% needs to > > > go into the commit message. > > > > We've been using these placeholders a lot in Renesas SoC-specific > > .dtsi files, as they allow us to introduce gradually support for a new SoC > > that is mounted on an existing PCB, and thus shares a board-specific > > .dtsi file. Hence I'm fine with this. > > Aye, if you're happy with it then I am too... > > > > However, I think more properties can be dropped from the placeholders. > > There is no need to have e.g. 'reg-names' and 'status = "disabled"' > > (there is no compatible value, so no matching is done). > > ...and this makes a lot of sense. I'd still like a comment in the > commit message though explaining why placeholder nodes are needed as > opposed to just leaving it blank etc. > I will drop the status and reg-names properties and also update the commit message while sending the v4 Cheers, Prabhakar
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi index fb6733f3cc2b..6d9db759a847 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi @@ -13,6 +13,14 @@ / { #address-cells = <2>; #size-cells = <2>; + audio_clk1: audio1-clk { + /* placeholder */ + }; + + audio_clk2: audio2-clk { + /* placeholder */ + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -54,6 +62,23 @@ soc: soc { #size-cells = <2>; ranges; + ssi1: ssi@1004a000 { + reg = <0 0x1004a000 0 0x400>; + #sound-dai-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + spi1: spi@1004b000 { + reg = <0 0x1004b000 0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; @@ -73,6 +98,48 @@ scif0: serial@1004b800 { status = "disabled"; }; + canfd: can@10050000 { + reg = <0 0x10050000 0 0x8000>; + status = "disabled"; + + /* placeholder */ + }; + + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058000 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058400 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + adc: adc@10059000 { + reg = <0 0x10059000 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + sbc: spi@10060000 { + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + status = "disabled"; + + /* placeholder */ + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g043-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -104,6 +171,95 @@ pinctrl: pinctrl@11030000 { <&cpg R9A07G043_GPIO_SPARE_RESETN>; }; + sdhi0: mmc@11c00000 { + reg = <0x0 0x11c00000 0 0x10000>; + status = "disabled"; + + /* placeholder */ + }; + + sdhi1: mmc@11c10000 { + reg = <0x0 0x11c10000 0 0x10000>; + status = "disabled"; + + /* placeholder */ + }; + + eth0: ethernet@11c20000 { + reg = <0 0x11c20000 0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + eth1: ethernet@11c30000 { + reg = <0 0x11c30000 0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + phyrst: usbphy-ctrl@11c40000 { + reg = <0 0x11c40000 0 0x10000>; + #reset-cells = <1>; + status = "disabled"; + + /* placeholder */ + }; + + ohci0: usb@11c50000 { + reg = <0 0x11c50000 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ohci1: usb@11c70000 { + reg = <0 0x11c70000 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ehci0: usb@11c50100 { + reg = <0 0x11c50100 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ehci1: usb@11c70100 { + reg = <0 0x11c70100 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + usb2_phy0: usb-phy@11c50200 { + reg = <0 0x11c50200 0 0x700>; + status = "disabled"; + + /* placeholder */ + }; + + usb2_phy1: usb-phy@11c70200 { + reg = <0 0x11c70200 0 0x700>; + status = "disabled"; + + /* placeholder */ + }; + + hsusb: usb@11c60000 { + reg = <0 0x11c60000 0 0x10000>; + status = "disabled"; + + /* placeholder */ + }; + plic: interrupt-controller@12c00000 { compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; #interrupt-cells = <2>; @@ -116,5 +272,26 @@ plic: interrupt-controller@12c00000 { resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; }; + + wdt0: watchdog@12800800 { + reg = <0 0x12800800 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + ostm1: timer@12801400 { + reg = <0x0 0x12801400 0x0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + ostm2: timer@12801800 { + reg = <0x0 0x12801800 0x0 0x400>; + status = "disabled"; + + /* placeholder */ + }; }; };