From patchwork Tue Sep 20 18:49:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 12982505 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 984C1C6FA97 for ; Tue, 20 Sep 2022 18:50:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231223AbiITSum (ORCPT ); Tue, 20 Sep 2022 14:50:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231190AbiITSuV (ORCPT ); Tue, 20 Sep 2022 14:50:21 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83FED5FF48; Tue, 20 Sep 2022 11:50:19 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id cc5so5946806wrb.6; Tue, 20 Sep 2022 11:50:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=EEV/bZNm0RhZpoNYETeZ7CWJmucOPEtVXdZB85ADqWM=; b=bnft1V8oxBH9jXg4qda8t6dZSmf3Iwfcf+cHXLuM06OoIfCrqXbnj2j2ZxXuYaMCN0 HqQ1l32q3nOwCIB4iqZxGpQk/6w2MikdnoAjXvVTbFxCF/OvWyLJYNQ9fjWRWFbgrHjI xVvx5aIKwLAn2jVdc9QltHkTcpmM42+czBY79snokGd1jOFXHSoskFNA4++EA7tu4XVA 3pQV06QRScJRRbclUxb2TbWcacmLfKD7VdnYB4gb/3Eio3JspcJykB1Hd5uZyihrMerq sSAjx8DbO6s6IibB39aL8NqWkCl5Q4UXMspkh0CnnbVr6s4iDJH1ZCeTDod7i4mM5O18 m8zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=EEV/bZNm0RhZpoNYETeZ7CWJmucOPEtVXdZB85ADqWM=; b=Lj2Scf1oRMhVB4nHVH8p9nH8rz6LU+IWVkmJBxpIK3DJwYkwHuNbEnCNTiPYWu/yj3 Q7DlZvSHlhbu2zsb5IvCi7sPJt7OQlJVK3YLqKEyEATtdt3SlVwWxRaQ31r7+pv2nUxm Vn9d4C48dkwmMl9RinJfU0vvV5BbRcdcXd6mQOrADfwzV4KJkAtTmQaMol5NtUauTNMh TR2IbB2TJ/0PsnalikApzv/sI2V0c3zqt9GAl7sAFXUMmtItZv+U3r6cnr5+Lly3CxuL /EbaxKNmigwW+Bt5x3EInJ0m4P8jlNz0iU5leRk2c1zgCm8zF/DNXjSV23l7sCqZCD1V kSSg== X-Gm-Message-State: ACrzQf0oHTiO0mQATHGWhr1Z2hgqWnpXrMZwyi+pVHwxowaXO6Sc/O5q kKFzIeJ/AlKrnOBF+hT620k= X-Google-Smtp-Source: AMsMyM65TgOSIr0ZfIgpLuog36rH44C9YuoCn+Yv9Tji2ryknGj6fK849OJKw3aT9oqGug0pAtWW/g== X-Received: by 2002:adf:f8ca:0:b0:226:e456:1896 with SMTP id f10-20020adff8ca000000b00226e4561896mr15181753wrq.177.1663699819115; Tue, 20 Sep 2022 11:50:19 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:e9a4:d6c9:505d:20d0]) by smtp.gmail.com with ESMTPSA id cc4-20020a5d5c04000000b00228de351fc0sm582722wrb.38.2022.09.20.11.50.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Sep 2022 11:50:18 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Conor Dooley Cc: Heiko Stuebner , Heinrich Schuchardt , Atish Patra , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v4 10/10] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Date: Tue, 20 Sep 2022 19:49:04 +0100 Message-Id: <20220920184904.90495-11-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Lad Prabhakar Enable Renesas RZ/Five SoC config in defconfig. It allows the default upstream kernel to boot on RZ/Five SMARC EVK board. Alongside enable SERIAL_SH_SCI config so that the serial driver used by RZ/Five SoC is built-in. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v3 -> v4 * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB tags with this change) * Used riscv instead of RISC-V in subject line v2 -> v3 * Included RB tags * Updated commit description v1 -> v2 * New patch --- arch/riscv/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 05fd5fcf24f9..97fba7884d7a 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_SOC_VIRT=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_R9A07G043=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_PM=y @@ -123,6 +125,7 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SH_SCI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y