diff mbox series

[RFC,7/7] arm64: dts: renesas: rzg2l-smarc: [HACK] Enable MTU3 PWM channel 3 for PWM mode 1 testing

Message ID 20220929103043.1228235-8-biju.das.jz@bp.renesas.com (mailing list archive)
State RFC
Delegated to: Geert Uytterhoeven
Headers show
Series Add RZ/G2L MTU3 PWM driver | expand

Commit Message

Biju Das Sept. 29, 2022, 10:30 a.m. UTC 
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../boot/dts/renesas/rz-smarc-common.dtsi     |  2 ++
 .../dts/renesas/rzg2l-smarc-pinfunction.dtsi  | 11 ++++++++++
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  |  5 +++++
 arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 20 +++++++++++++++++++
 4 files changed, 38 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
index 3962d47b3e59..1414cc8e99ca 100644
--- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
@@ -160,12 +160,14 @@  &sdhi1 {
 	status = "okay";
 };
 
+#if 0
 &spi1 {
 	pinctrl-0 = <&spi1_pins>;
 	pinctrl-names = "default";
 
 	status = "okay";
 };
+#endif
 
 &usb2_phy0 {
 	pinctrl-0 = <&usb0_pins>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
index bd81028d5462..40772bde9d05 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -64,6 +64,15 @@  mtu3_clk {
 			pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */
 				 <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTLCKB */
 		};
+
+		mtu3_pwm {
+			pinmux =
+
+				<RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */
+				<RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */
+				<RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */
+				<RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */
+		};
 	};
 #endif
 
@@ -125,12 +134,14 @@  sound_clk_pins: sound_clk {
 		input-enable;
 	};
 
+#if 0
 	spi1_pins: spi1 {
 		pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
 			 <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
 			 <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
 			 <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
 	};
+#endif
 
 	ssi0_pins: ssi0 {
 		pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 6ce6e9434873..b9f8f1759fce 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -62,6 +62,11 @@  counter@1 {
 	counter@2 {
 		status = "okay";
 	};
+
+	pwm@3 {
+		renesas,pwm-mode1;
+		status = "okay";
+	};
 };
 #endif
 
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index 6be25a8a28db..f17428c5826d 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -18,6 +18,8 @@ 
  * Please change below macros according to SW1 setting
  */
 
+#define MTU3_PHASE_COUNTING_SUPPORT	1
+
 #define SW_SD0_DEV_SEL	1
 
 #define SW_SCIF_CAN	0
@@ -78,6 +80,24 @@  wm8978: codec@1a {
 	};
 };
 
+#if (MTU3_PHASE_COUNTING_SUPPORT)
+&mtu3 {
+	status = "okay";
+	counter@1 {
+		status = "okay";
+	};
+
+	counter@2 {
+		status = "okay";
+	};
+
+	pwm@3 {
+		renesas,pwm-mode1;
+		status = "okay";
+	};
+};
+#endif
+
 /*
  * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
  * SW1 should be at position 2->3 so that SER0_CTS# line is activated