| Message ID | 20221003223222.448551-2-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | AX45MP: Add support to non-coherent DMA | expand |
Hi Prabhakar, On Tue, Oct 4, 2022 at 12:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > describes the L2 cache block. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml Not andestech,ax45mp-cache.yaml? > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (C) 2022 Renesas Electronics Corp. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/renesas/r9a07g043f-l2-cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive L2 Cache Controller Andestech AX45MP? > + > +maintainers: > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > + > +description: > + A level-2 cache (L2C) is used to improve the system performance by providing > + a larger amount of cache line entries and reasonable access delays. The L2C > + is shared between cores, and a non-inclusive non-exclusive policy is used. > + > +properties: > + compatible: > + items: > + - const: andestech,ax45mp-cache > + - const: cache This makes the schema apply to any node which is compatible with "cache", cfr. the report from Rob's bot. You need a select block to avoid that, cfr. Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thank you for the review. On Tue, Oct 4, 2022 at 7:42 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Tue, Oct 4, 2022 at 12:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > describes the L2 cache block. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml > > Not andestech,ax45mp-cache.yaml? > I wasn't sure as we were including this in soc/renesas so named it as r9a07g043f-l2-cache.yaml if there are no issues I'll rename it andestech,ax45mp-cache.yaml. > > @@ -0,0 +1,82 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +# Copyright (C) 2022 Renesas Electronics Corp. > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/soc/renesas/r9a07g043f-l2-cache.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: SiFive L2 Cache Controller > > Andestech AX45MP? > Ouch! > > + > > +maintainers: > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > + > > +description: > > + A level-2 cache (L2C) is used to improve the system performance by providing > > + a larger amount of cache line entries and reasonable access delays. The L2C > > + is shared between cores, and a non-inclusive non-exclusive policy is used. > > + > > +properties: > > + compatible: > > + items: > > + - const: andestech,ax45mp-cache > > + - const: cache > > This makes the schema apply to any node which is compatible with > "cache", cfr. the report from Rob's bot. > Actually dt_binding_check didn't complain when I ran it locally (maybe it's time to update dt-schema). > You need a select block to avoid that, cfr. > Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml. > Thanks for the pointer. Cheers, Prabhakar
On Tue, Oct 04, 2022 at 08:26:01AM +0100, Lad, Prabhakar wrote: > Hi Geert, > > Thank you for the review. > > On Tue, Oct 4, 2022 at 7:42 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > > Hi Prabhakar, > > > > On Tue, Oct 4, 2022 at 12:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > > describes the L2 cache block. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Thanks for your patch! > > > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml > > > > Not andestech,ax45mp-cache.yaml? > > > I wasn't sure as we were including this in soc/renesas so named it as > r9a07g043f-l2-cache.yaml if there are no issues I'll rename it > andestech,ax45mp-cache.yaml. I may be guilty of suggesting soc/renesas in the first place, but should this maybe be in soc/andestech? I have no skin in the game, so at the end of the day it doesnt matter to me, but I would imagine that you're not going to be the only users of this l2 cache? Or is it a case of "we will deal with future users when said future users arrive"? But either way, naming it after the less specific compatible makes more sense to me. Thanks, Conor.
On Mon, Oct 03, 2022 at 11:32:21PM +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > describes the L2 cache block. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > .../soc/renesas/r9a07g043f-l2-cache.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml > > diff --git a/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml > new file mode 100644 > index 000000000000..f96eeffa58ce > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (C) 2022 Renesas Electronics Corp. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/renesas/r9a07g043f-l2-cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive L2 Cache Controller > + > +maintainers: > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > + > +description: > + A level-2 cache (L2C) is used to improve the system performance by providing > + a larger amount of cache line entries and reasonable access delays. The L2C > + is shared between cores, and a non-inclusive non-exclusive policy is used. > + > +properties: > + compatible: > + items: > + - const: andestech,ax45mp-cache > + - const: cache I think preemptively adding a "renesas,r9a07g043f-l2-cache" here is a good idea, just in case something crops up down the line. Thanks, Conor. > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + cache-line-size: > + const: 64 > + > + cache-level: > + const: 2 > + > + cache-sets: > + const: 1024 > + > + cache-size: > + enum: [131072, 262144, 524288, 1048576, 2097152] > + > + cache-unified: true > + > + next-level-cache: true > + > + pma-regions: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + minItems: 1 > + maxItems: 16 > + description: Optional array of memory regions to be set as non-cacheable > + bufferable regions which will be setup in the PMA. > + > +additionalProperties: false > + > +required: > + - compatible > + - cache-line-size > + - cache-level > + - cache-sets > + - cache-size > + - cache-unified > + - interrupts > + - reg > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + > + cache-controller@2010000 { > + reg = <0x13400000 0x100000>; > + compatible = "andestech,ax45mp-cache", "cache"; > + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; > + cache-line-size = <64>; > + cache-level = <2>; > + cache-sets = <1024>; > + cache-size = <262144>; > + cache-unified; > + pma-regions = <0x00000000 0x10000000>, > + <0x10000000 0x04000000>, > + <0x20000000 0x10000000>, > + <0x58000000 0x08000000>; > + }; > -- > 2.25.1 >
On Tue, Oct 4, 2022 at 8:32 AM Conor Dooley <conor.dooley@microchip.com> wrote: > > On Tue, Oct 04, 2022 at 08:26:01AM +0100, Lad, Prabhakar wrote: > > Hi Geert, > > > > Thank you for the review. > > > > On Tue, Oct 4, 2022 at 7:42 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > > > > Hi Prabhakar, > > > > > > On Tue, Oct 4, 2022 at 12:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > > > describes the L2 cache block. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Thanks for your patch! > > > > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml > > > > > > Not andestech,ax45mp-cache.yaml? > > > > > I wasn't sure as we were including this in soc/renesas so named it as > > r9a07g043f-l2-cache.yaml if there are no issues I'll rename it > > andestech,ax45mp-cache.yaml. > > I may be guilty of suggesting soc/renesas in the first place, but should > this maybe be in soc/andestech? I have no skin in the game, so at the > end of the day it doesnt matter to me, but I would imagine that you're > not going to be the only users of this l2 cache? Or is it a case of "we > will deal with future users when said future users arrive"? But either > way, naming it after the less specific compatible makes more sense to > me. > As there aren't any Andestech SoCs upstream, I am in favour of keeping in soc/renesas for maintenance. If in future there comes a new soc from Andestech (which will go into soc/andestech) we will have to split the maintenance work. But anyway if there will be any users of L2 cache we could always provide a config option which can be used by other SoCs. Said that I'll let Geert decide on this. Cheers, Prabhakar
Hi Prabhakar, On Tue, Oct 4, 2022 at 9:59 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Tue, Oct 4, 2022 at 8:32 AM Conor Dooley <conor.dooley@microchip.com> wrote: > > On Tue, Oct 04, 2022 at 08:26:01AM +0100, Lad, Prabhakar wrote: > > > On Tue, Oct 4, 2022 at 7:42 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > > On Tue, Oct 4, 2022 at 12:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > > > > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > > > > describes the L2 cache block. > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Thanks for your patch! > > > > > > > > > --- /dev/null > > > > > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml > > > > > > > > Not andestech,ax45mp-cache.yaml? > > > > > > > I wasn't sure as we were including this in soc/renesas so named it as > > > r9a07g043f-l2-cache.yaml if there are no issues I'll rename it > > > andestech,ax45mp-cache.yaml. > > > > I may be guilty of suggesting soc/renesas in the first place, but should > > this maybe be in soc/andestech? I have no skin in the game, so at the > > end of the day it doesnt matter to me, but I would imagine that you're > > not going to be the only users of this l2 cache? Or is it a case of "we > > will deal with future users when said future users arrive"? But either > > way, naming it after the less specific compatible makes more sense to > > me. > > > As there aren't any Andestech SoCs upstream, I am in favour of keeping > in soc/renesas for maintenance. If in future there comes a new soc > from Andestech (which will go into soc/andestech) we will have to > split the maintenance work. > But anyway if there will be any users of L2 cache we could always > provide a config option which can be used by other SoCs. What about Documentation/devicetree/bindings/cache/? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
HI Geert, On Tue, Oct 4, 2022 at 10:12 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Tue, Oct 4, 2022 at 9:59 AM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Tue, Oct 4, 2022 at 8:32 AM Conor Dooley <conor.dooley@microchip.com> wrote: > > > On Tue, Oct 04, 2022 at 08:26:01AM +0100, Lad, Prabhakar wrote: > > > > On Tue, Oct 4, 2022 at 7:42 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > > > On Tue, Oct 4, 2022 at 12:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > > > > > > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > > > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > > > > > describes the L2 cache block. > > > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > Thanks for your patch! > > > > > > > > > > > --- /dev/null > > > > > > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml > > > > > > > > > > Not andestech,ax45mp-cache.yaml? > > > > > > > > > I wasn't sure as we were including this in soc/renesas so named it as > > > > r9a07g043f-l2-cache.yaml if there are no issues I'll rename it > > > > andestech,ax45mp-cache.yaml. > > > > > > I may be guilty of suggesting soc/renesas in the first place, but should > > > this maybe be in soc/andestech? I have no skin in the game, so at the > > > end of the day it doesnt matter to me, but I would imagine that you're > > > not going to be the only users of this l2 cache? Or is it a case of "we > > > will deal with future users when said future users arrive"? But either > > > way, naming it after the less specific compatible makes more sense to > > > me. > > > > > As there aren't any Andestech SoCs upstream, I am in favour of keeping > > in soc/renesas for maintenance. If in future there comes a new soc > > from Andestech (which will go into soc/andestech) we will have to > > split the maintenance work. > > But anyway if there will be any users of L2 cache we could always > > provide a config option which can be used by other SoCs. > > What about Documentation/devicetree/bindings/cache/? > Sounds good to me. Cheers, Prabhakar
diff --git a/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml new file mode 100644 index 000000000000..f96eeffa58ce --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/r9a07g043f-l2-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive L2 Cache Controller + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + A level-2 cache (L2C) is used to improve the system performance by providing + a larger amount of cache line entries and reasonable access delays. The L2C + is shared between cores, and a non-inclusive non-exclusive policy is used. + +properties: + compatible: + items: + - const: andestech,ax45mp-cache + - const: cache + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cache-line-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + enum: [131072, 262144, 524288, 1048576, 2097152] + + cache-unified: true + + next-level-cache: true + + pma-regions: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 16 + description: Optional array of memory regions to be set as non-cacheable + bufferable regions which will be setup in the PMA. + +additionalProperties: false + +required: + - compatible + - cache-line-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - interrupts + - reg + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + cache-controller@2010000 { + reg = <0x13400000 0x100000>; + compatible = "andestech,ax45mp-cache", "cache"; + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <262144>; + cache-unified; + pma-regions = <0x00000000 0x10000000>, + <0x10000000 0x04000000>, + <0x20000000 0x10000000>, + <0x58000000 0x08000000>; + };