| Message ID | 20221028165921.94487-2-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 57e1b873c2f54253f4c81bddb782e183ee6544ae |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add support for Renesas RZ/Five SoC | expand |
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Sort the CPU cores list alphabetically for maintenance. Reviewed-by: Guo Ren <guoren@kernel.org> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > --- > v4 -> v5 > * Included RB tag from Conor > > v3 -> v4 > * Included RB tag from Heiko > > v2 -> v3 > * Included RB tag from Geert > > v1 -> v2 > * Included RB tag from Krzysztof > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 90a7cabf58fe..ae7963e99225 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -28,17 +28,17 @@ properties: > oneOf: > - items: > - enum: > - - sifive,rocket0 > + - canaan,k210 > - sifive,bullet0 > - sifive,e5 > - sifive,e7 > - sifive,e71 > - - sifive,u74-mc > - - sifive,u54 > - - sifive,u74 > + - sifive,rocket0 > - sifive,u5 > + - sifive,u54 > - sifive,u7 > - - canaan,k210 > + - sifive,u74 > + - sifive,u74-mc > - const: riscv > - items: > - enum: > -- > 2.25.1 >
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 90a7cabf58fe..ae7963e99225 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -28,17 +28,17 @@ properties: oneOf: - items: - enum: - - sifive,rocket0 + - canaan,k210 - sifive,bullet0 - sifive,e5 - sifive,e7 - sifive,e71 - - sifive,u74-mc - - sifive,u54 - - sifive,u74 + - sifive,rocket0 - sifive,u5 + - sifive,u54 - sifive,u7 - - canaan,k210 + - sifive,u74 + - sifive,u74-mc - const: riscv - items: - enum: