| Message ID | 20221103143440.46449-5-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 64416ef0b0c4d73349035d1b3206eed3d2047ee0 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | r8a779f0: update SCIF parent clocks | expand |
On Thu, Nov 3, 2022 at 3:34 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > As serial communication requires a clock signal, the Serial clean clock > Communication Interfaces with FIFO (SCIF) are clocked by a clock that > is not affected by Spread Spectrum or Fractional Multiplication. > > Hence change the clock input for the SCIF Baud Rate Generator internal > clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the > same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81. > > Fixes: c62331e8222f ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support") > Fixes: 40753144256b ("arm64: dts: renesas: r8a779f0: Add SCIF nodes") > Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.2, with the above fixed. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 3be577dc9a93..4092c0016035 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -657,7 +657,7 @@ scif0: serial@e6e60000 { reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x51>, <&dmac0 0x50>, @@ -674,7 +674,7 @@ scif1: serial@e6e68000 { reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x53>, <&dmac0 0x52>, @@ -691,7 +691,7 @@ scif3: serial@e6c50000 { reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 704>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x57>, <&dmac0 0x56>, @@ -708,7 +708,7 @@ scif4: serial@e6c40000 { reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 705>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>,
As serial communication requires a clock signal, the Serial Communication Interfaces with FIFO (SCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the clock input for the SCIF Baud Rate Generator internal clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81. Fixes: c62331e8222f ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support") Fixes: 40753144256b ("arm64: dts: renesas: r8a779f0: Add SCIF nodes") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)