From patchwork Mon Nov 7 15:56:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13034603 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E916FC4332F for ; Mon, 7 Nov 2022 16:07:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232865AbiKGQHz (ORCPT ); Mon, 7 Nov 2022 11:07:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232766AbiKGQHg (ORCPT ); Mon, 7 Nov 2022 11:07:36 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 24EC220BEC; Mon, 7 Nov 2022 08:07:17 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 14AAC139F; Mon, 7 Nov 2022 08:07:23 -0800 (PST) Received: from pierre123.arm.com (pierre123.nice.arm.com [10.34.100.128]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DE0053F534; Mon, 7 Nov 2022 08:07:01 -0800 (PST) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Pierre Gondois , Rob Herring , Krzysztof Kozlowski , Florian Fainelli , Broadcom internal kernel review list , Ray Jui , Scott Branden , Tsahee Zidenberg , Antoine Tenart , Brijesh Singh , Suravee Suthikulpanit , Tom Lendacky , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Khuong Dinh , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , William Zhang , Anand Gore , Kursad Oney , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Alim Akhtar , Shawn Guo , Li Yang , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Chester Lin , =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger , NXP S32 Linux Team , Wei Xu , Chanho Min , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Lars Povlsen , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Thierry Reding , Jonathan Hunter , Andy Gross , Bjorn Andersson , Konrad Dybcio , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Kunihiko Hayashi , Masami Hiramatsu , Jisheng Zhang , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Viorel Suman , Abel Vesa , Zhou Peng , Shenwei Wang , Ming Qian , Peng Fan , Tim Harvey , Adam Ford , Lucas Stach , Richard Zhu , Li Jun , Markus Niebel , Joakim Zhang , Marek Vasut , Laurent Pinchart , Paul Elder , Alexander Stein , Martin Kepplinger , David Heidelberg , Liu Ying , Oliver Graute , Dong Aisheng , Wei Fang , Clark Wang , Jacky Bai , Chris Packham , Vadym Kochan , Sameer Pujar , Prathamesh Shete , Mikko Perttunen , Akhil R , Sumit Gupta , Diogo Ivo , Vidya Sagar , Ashish Mhetre , Johan Jonker , Christopher Obbard , Ezequiel Garcia , Aswani Reddy , Shashank Prashar , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-mediatek@lists.infradead.org, openbmc@lists.ozlabs.org, linux-tegra@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-realtek-soc@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 02/23] arm64: dts: Update cache properties for amd Date: Mon, 7 Nov 2022 16:56:55 +0100 Message-Id: <20221107155825.1644604-3-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221107155825.1644604-1-pierre.gondois@arm.com> References: <20221107155825.1644604-1-pierre.gondois@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois Acked-by: Tom Lendacky --- arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi index 93688a0b6820..9f2d983e082d 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi @@ -163,38 +163,47 @@ CPU7: cpu@301 { }; L2_0: l2-cache0 { + compatible = "cache"; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; cache-unified; + cache-level = <2>; next-level-cache = <&L3>; }; L2_1: l2-cache1 { + compatible = "cache"; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; cache-unified; + cache-level = <2>; next-level-cache = <&L3>; }; L2_2: l2-cache2 { + compatible = "cache"; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; cache-unified; + cache-level = <2>; next-level-cache = <&L3>; }; L2_3: l2-cache3 { + compatible = "cache"; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; cache-unified; + cache-level = <2>; next-level-cache = <&L3>; }; L3: l3-cache { + compatible = "cache"; cache-level = <3>; cache-size = <0x800000>; cache-line-size = <64>;