From patchwork Thu Nov 17 12:25:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 13046698 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CE1BC4332F for ; Thu, 17 Nov 2022 12:26:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240099AbiKQM0Q (ORCPT ); Thu, 17 Nov 2022 07:26:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240076AbiKQM0O (ORCPT ); Thu, 17 Nov 2022 07:26:14 -0500 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23749193C3; Thu, 17 Nov 2022 04:26:13 -0800 (PST) Received: from desky.lan (91-154-32-225.elisa-laajakaista.fi [91.154.32.225]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 292B8133C; Thu, 17 Nov 2022 13:26:09 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1668687970; bh=Yp9gIE748wlY7gw+8HNjk6NkwSOWfjoqB6wxFtfVN+E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HaSo4pZYzoo3itwKO8/m3/xpjHeFZskjJfImSF+RUvW0Zcx0vkUNqVPgQeXNK9c6K UkyDKN5+ahKf5ZJSYDHvcYWB60ORAeHZctQe82HG+KQOmZTrubGP0hRYDnM1S7kIil N0BYiZk+WdR+Oa8LCzVZauTzhDrMPazmQtg2YuzI= From: Tomi Valkeinen To: Laurent Pinchart , Kieran Bingham , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Jonas Karlman , Jernej Skrabec , Tomi Valkeinen Subject: [PATCH v1 3/8] clk: renesas: r8a779g0: Add display related clocks Date: Thu, 17 Nov 2022 14:25:42 +0200 Message-Id: <20221117122547.809644-4-tomi.valkeinen@ideasonboard.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221117122547.809644-1-tomi.valkeinen@ideasonboard.com> References: <20221117122547.809644-1-tomi.valkeinen@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Tomi Valkeinen Add clocks related to display which are needed to get the DSI output working. Extracted from Renesas BSP tree. Signed-off-by: Tomi Valkeinen Reviewed-by: Kieran Bingham Reviewed-by: Laurent Pinchart --- drivers/clk/renesas/r8a779g0-cpg-mssr.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index c6337a408e5e..6937f1aee677 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -145,6 +145,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1), DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1), + DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), + DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870), DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870), @@ -161,6 +163,14 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC), + + DEF_MOD("dis0", 411, R8A779G0_CLK_S0D3), + DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_DSIREF), + DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_DSIREF), + + DEF_MOD("fcpvd0", 508, R8A779G0_CLK_S0D3), + DEF_MOD("fcpvd1", 509, R8A779G0_CLK_S0D3), + DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1), @@ -193,6 +203,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2), DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2), DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4), + + DEF_MOD("vspd0", 830, R8A779G0_CLK_S0D1_VIO), + DEF_MOD("vspd1", 831, R8A779G0_CLK_S0D1_VIO), + DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R), DEF_MOD("cmt0", 910, R8A779G0_CLK_R), DEF_MOD("cmt1", 911, R8A779G0_CLK_R),