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Thu, 24 Nov 2022 09:22:43 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guo Ren Cc: Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH DO NOT REVIEW v4 4/7] riscv: errata: andes: Fix auipc-jalr addresses in patched alternatives Date: Thu, 24 Nov 2022 17:22:04 +0000 Message-Id: <20221124172207.153718-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Lad Prabhakar This patch is added just for building purpose, as patch [0] will export this in its next version. https://patchwork.kernel.org/project/linux-riscv/patch/20221110164924.529386-6-heiko@sntech.de/ Signed-off-by: Lad Prabhakar --- Note, as Heiko will be exporting riscv_alternative_fix_auipc_jalr() function so that it can be used other erratas Ive just included for compilation. --- arch/riscv/errata/andes/errata.c | 71 ++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c index ec3e052ca8c7..4061ad4983bc 100644 --- a/arch/riscv/errata/andes/errata.c +++ b/arch/riscv/errata/andes/errata.c @@ -13,9 +13,80 @@ #include #include #include +#include #include +#include #include +/* Copy of Heiko's code from patch [0] + * [0] https://patchwork.kernel.org/project/linux-riscv/patch/20221110164924.529386-6-heiko@sntech.de/ + */ +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) + +static inline bool is_auipc_jalr_pair(long insn1, long insn2) +{ + return is_auipc_insn(insn1) && is_jalr_insn(insn2); +} + +#define JALR_SIGN_MASK BIT(I_IMM_SIGN_OPOFF - I_IMM_11_0_OPOFF) +#define JALR_OFFSET_MASK I_IMM_11_0_MASK +#define AUIPC_OFFSET_MASK U_IMM_31_12_MASK +#define AUIPC_PAD (0x00001000) +#define JALR_SHIFT I_IMM_11_0_OPOFF + +#define to_jalr_imm(offset) \ + ((offset & I_IMM_11_0_MASK) << I_IMM_11_0_OPOFF) + +#define to_auipc_imm(offset) \ + ((offset & JALR_SIGN_MASK) ? \ + ((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) : \ + (offset & AUIPC_OFFSET_MASK)) + +static void riscv_alternative_fix_auipc_jalr(unsigned int *alt_ptr, + unsigned int len, int patch_offset) +{ + int num_instr = len / sizeof(u32); + unsigned int call[2]; + int i; + int imm1; + u32 rd1; + + for (i = 0; i < num_instr; i++) { + /* is there a further instruction? */ + if (i + 1 >= num_instr) + continue; + + if (!is_auipc_jalr_pair(*(alt_ptr + i), *(alt_ptr + i + 1))) + continue; + + /* call will use ra register */ + rd1 = EXTRACT_RD_REG(*(alt_ptr + i)); + if (rd1 != 1) + continue; + + /* get and adjust new target address */ + imm1 = EXTRACT_UTYPE_IMM(*(alt_ptr + i)); + imm1 += EXTRACT_ITYPE_IMM(*(alt_ptr + i + 1)); + imm1 -= patch_offset; + + /* pick the original auipc + jalr */ + call[0] = *(alt_ptr + i); + call[1] = *(alt_ptr + i + 1); + + /* drop the old IMMs */ + call[0] &= ~(U_IMM_31_12_MASK); + call[1] &= ~(I_IMM_11_0_MASK << I_IMM_11_0_OPOFF); + + /* add the adapted IMMs */ + call[0] |= to_auipc_imm(imm1); + call[1] |= to_jalr_imm(imm1); + + /* patch the call place again */ + patch_text_nosync(alt_ptr + i, call, 8); + } +} + static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid) { if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO))