| Message ID | 20221213230129.549968-5-fabrizio.castro.jz@renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 36aa3eee39b2bce5596d3a1178d3c381c1cf3b57 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | SDHI/MMC SoC support for the RZ/V2M | expand |
Hi Fabrizio, On Wed, Dec 14, 2022 at 12:02 AM Fabrizio Castro <fabrizio.castro.jz@renesas.com> wrote: > The RZ/V2M comes with 2 SDHI interfaces and 1 eMMC interface. > Add the relevant nodes to the SoC specific device tree. > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.3. Note that this causes "make dtbs_check" failures, due to a bug in the bindings. I have sent a fix. https://lore.kernel.org/054c9f4dbb0bb1525f780d1e85c724436465c20c.1673270716.git.geert+renesas@glider.be Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, > > Hi Fabrizio, > > On Wed, Dec 14, 2022 at 12:02 AM Fabrizio Castro > <fabrizio.castro.jz@renesas.com> wrote: > > The RZ/V2M comes with 2 SDHI interfaces and 1 eMMC interface. > > Add the relevant nodes to the SoC specific device tree. > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will queue in renesas-devel for v6.3. > > Note that this causes "make dtbs_check" failures, due to a bug in > the bindings. I have sent a fix. > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ker > nel.org%2F054c9f4dbb0bb1525f780d1e85c724436465c20c.1673270716.git.geert%2B > renesas%40glider.be&data=05%7C01%7Cfabrizio.castro.jz%40renesas.com%7Cb621 > 0a13c0e64f5719a408daf245694d%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C > 638088677177461554%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2l > uMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=cHhpiy1cwPTiri2I > l1j7Ck6iwR9DEdvlc8egJDBc2cM%3D&reserved=0 Thanks for that! Fab > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But > when I'm talking to journalists I just say "programmer" or something like > that. > -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 0373ec409d54..dd35a8ff72ee 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -69,6 +69,54 @@ gic: interrupt-controller@82010000 { clock-names = "clk"; }; + sdhi0: mmc@85000000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85000000 0 0x2000>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>, + <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>, + <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>, + <&cpg CPG_MOD R9A09G011_SDI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_SDI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@85010000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85010000 0 0x2000>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>, + <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>, + <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>, + <&cpg CPG_MOD R9A09G011_SDI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_SDI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + emmc: mmc@85020000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85020000 0 0x2000>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>, + <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>, + <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>, + <&cpg CPG_MOD R9A09G011_EMM_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_EMM_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + avb: ethernet@a3300000 { compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; reg = <0 0xa3300000 0 0x800>;
The RZ/V2M comes with 2 SDHI interfaces and 1 eMMC interface. Add the relevant nodes to the SoC specific device tree. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+)