From patchwork Tue Mar 21 11:47:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13182652 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2E6DC74A5B for ; Tue, 21 Mar 2023 11:48:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230408AbjCULsa (ORCPT ); Tue, 21 Mar 2023 07:48:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230387AbjCULsW (ORCPT ); Tue, 21 Mar 2023 07:48:22 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 94D104AD25; Tue, 21 Mar 2023 04:48:16 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,278,1673881200"; d="scan'208";a="156652151" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Mar 2023 20:48:16 +0900 Received: from localhost.localdomain (unknown [10.226.93.140]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9224F41E3338; Tue, 21 Mar 2023 20:48:13 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad Subject: [PATCH v4 5/5] arm64: dts: renesas: r9a07g044: Enable sci0 node using dt overlay Date: Tue, 21 Mar 2023 11:47:53 +0000 Message-Id: <20230321114753.75038-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230321114753.75038-1-biju.das.jz@bp.renesas.com> References: <20230321114753.75038-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Enable sci0 node using dt overlay and disable can{0,1}-stb-hog nodes in dt overlay as its pins are shared with sci0 pins. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v3->v4: * Updated commit header sci0 nodes->sci0 node * Removed PMOD USBUART reference and connection details as user can connect anything on that PMOD1 pins. * Renamed r9a07g043-smarc.dtso->r9a07g043-smarc-pmod.dtso * Dropped unused header file dt-bindings/gpio/gpio.h v3: * New patch --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../dts/renesas/r9a07g043-smarc-pmod.dtso | 42 +++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 23b10c03091c..d1f10ae85f9f 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso b/arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso new file mode 100644 index 000000000000..b125a1152982 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/{G2UL, Five} SMARC EVK PMOD parts + * + * Copyright (C) 2023 Renesas Electronics Corp. + * + * + * [Connection] + * + * SMARC EVK + * +----------------------------+ + * |CN7 (PMOD1 PIN HEADER) | + * | SCI0_TXD pin7 | + * | SCI0_RXD pin8 | + * +----------------------------+ + * + */ + +/dts-v1/; +/plugin/; +#include + +&pinctrl { + can0-stb-hog { + status = "disabled"; + }; + + can1-stb-hog { + status = "disabled"; + }; + + sci0_pins: sci0-pins { + pinmux = , /* TxD */ + ; /* RxD */ + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_pins>; + pinctrl-names = "default"; + status = "okay"; +};