Message ID | 20230525084823.4195-3-wsa+renesas@sang-engineering.com (mailing list archive) |
---|---|
State | Mainlined |
Commit | c776a2128dee50a9f10eace4a14ff894e1432a31 |
Delegated to: | Geert Uytterhoeven |
Headers | show |
Series | KingFisher: fix SCIF1, add HSCIF1 | expand |
On Thu, May 25, 2023 at 10:48 AM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Exposed on CN4. Tested by connecting it to a Renesas Ebisu board. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Thanks, will queue in renesas-devel for v6.5. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 4c6d50acfab1..e62f5359f64b 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -10,6 +10,7 @@ / { aliases { serial1 = &hscif0; serial2 = &scif1; + serial3 = &hscif1; mmc2 = &sdhi3; }; @@ -132,6 +133,14 @@ &hscif0 { status = "okay"; }; +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + status = "okay"; +}; + &hsusb { dr_mode = "otg"; status = "okay"; @@ -387,6 +396,11 @@ hscif0_pins: hscif0 { function = "hscif0"; }; + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + scif1_pins: scif1 { groups = "scif1_data_b"; function = "scif1";