From patchwork Fri Jun 30 16:17:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13298447 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3BDDEB64DC for ; Fri, 30 Jun 2023 16:18:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232538AbjF3QRt (ORCPT ); Fri, 30 Jun 2023 12:17:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232383AbjF3QR2 (ORCPT ); Fri, 30 Jun 2023 12:17:28 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B1CDB3ABC; Fri, 30 Jun 2023 09:17:27 -0700 (PDT) X-IronPort-AV: E=Sophos;i="6.01,171,1684767600"; d="scan'208";a="166246347" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 01 Jul 2023 01:17:27 +0900 Received: from localhost.localdomain (unknown [10.226.93.15]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 4FF0B4015EE4; Sat, 1 Jul 2023 01:17:25 +0900 (JST) From: Biju Das To: Vinod Koul Cc: Hien Huynh , Biju Das , Geert Uytterhoeven , Lad Prabhakar , dmaengine@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 2/2] dma: rz-dmac: Fix destination and source data size setting Date: Fri, 30 Jun 2023 17:17:16 +0100 Message-Id: <20230630161716.586552-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230630161716.586552-1-biju.das.jz@bp.renesas.com> References: <20230630161716.586552-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Hien Huynh Before setting DDS and SDS values, we need to clear its value first otherwise, we get incorrect results when we change/update the DMA bus width several times due to the 'OR' expression. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Signed-off-by: Hien Huynh Signed-off-by: Biju Das --- v1->v2: * Updated patch header. --- drivers/dma/sh/rz-dmac.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 229f642fde6b..331ea80f21b0 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -145,8 +145,10 @@ struct rz_dmac { #define CHCFG_REQD BIT(3) #define CHCFG_SEL(bits) ((bits) & 0x07) #define CHCFG_MEM_COPY (0x80400008) -#define CHCFG_FILL_DDS(a) (((a) << 16) & GENMASK(19, 16)) -#define CHCFG_FILL_SDS(a) (((a) << 12) & GENMASK(15, 12)) +#define CHCFG_FILL_DDS_MASK GENMASK(19, 16) +#define CHCFG_FILL_DDS(a) (((a) << 16) & CHCFG_FILL_DDS_MASK) +#define CHCFG_FILL_SDS_MASK GENMASK(15, 12) +#define CHCFG_FILL_SDS(a) (((a) << 12) & CHCFG_FILL_SDS_MASK) #define CHCFG_FILL_TM(a) (((a) & BIT(5)) << 22) #define CHCFG_FILL_AM(a) (((a) & GENMASK(4, 2)) << 6) #define CHCFG_FILL_LVL(a) (((a) & BIT(1)) << 5) @@ -607,12 +609,14 @@ static int rz_dmac_config(struct dma_chan *chan, if (val == CHCFG_DS_INVALID) return -EINVAL; + channel->chcfg &= ~CHCFG_FILL_DDS_MASK; channel->chcfg |= CHCFG_FILL_DDS(val); val = rz_dmac_ds_to_val_mapping(config->src_addr_width); if (val == CHCFG_DS_INVALID) return -EINVAL; + channel->chcfg &= ~CHCFG_FILL_SDS_MASK; channel->chcfg |= CHCFG_FILL_SDS(val); return 0;