| Message ID | 20230721074452.65545-2-yoshihiro.shimoda.uh@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | PCI: rcar-gen4: Add R-Car Gen4 PCIe support | expand |
On Fri, Jul 21, 2023 at 04:44:33PM +0900, Yoshihiro Shimoda wrote: > Add "Message Routing" and "INTx Mechanism Messages" macros to enable > a PCIe driver to send messages for INTx Interrupt Signaling. > > The "Message Routing" is from Table 2-17, and the "INTx Mechanism > Messages" is from Table 2-18 on the PCI Express Base Specification, > Rev. 4.0 Version 1.0. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > Reviewed-by: Serge Semin <fancer.lancer@gmail.com> > --- > drivers/pci/pci.h | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index a4c397434057..0b6df6c2c918 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -13,6 +13,24 @@ > > #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 > > +/* Message Routing (r[2:0]) */ > +#define PCI_MSG_TYPE_R_ROUTING_RC 0 > +#define PCI_MSG_TYPE_R_ROUTING_ADDR 1 > +#define PCI_MSG_TYPE_R_ROUTING_ID 2 > +#define PCI_MSG_TYPE_R_ROUTING_BC 3 > +#define PCI_MSG_TYPE_R_ROUTING_LOCAL 4 > +#define PCI_MSG_TYPE_R_ROUTING_GATHER 5 > + > +/* INTx Mechanism Messages */ > +#define PCI_MSG_CODE_ASSERT_INTA 0x20 > +#define PCI_MSG_CODE_ASSERT_INTB 0x21 > +#define PCI_MSG_CODE_ASSERT_INTC 0x22 > +#define PCI_MSG_CODE_ASSERT_INTD 0x23 > +#define PCI_MSG_CODE_DEASSERT_INTA 0x24 > +#define PCI_MSG_CODE_DEASSERT_INTB 0x25 > +#define PCI_MSG_CODE_DEASSERT_INTC 0x26 > +#define PCI_MSG_CODE_DEASSERT_INTD 0x27 > + > extern const unsigned char pcie_link_speed[]; > extern bool pci_early_dump; > > -- > 2.25.1 >
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index a4c397434057..0b6df6c2c918 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -13,6 +13,24 @@ #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 +/* Message Routing (r[2:0]) */ +#define PCI_MSG_TYPE_R_ROUTING_RC 0 +#define PCI_MSG_TYPE_R_ROUTING_ADDR 1 +#define PCI_MSG_TYPE_R_ROUTING_ID 2 +#define PCI_MSG_TYPE_R_ROUTING_BC 3 +#define PCI_MSG_TYPE_R_ROUTING_LOCAL 4 +#define PCI_MSG_TYPE_R_ROUTING_GATHER 5 + +/* INTx Mechanism Messages */ +#define PCI_MSG_CODE_ASSERT_INTA 0x20 +#define PCI_MSG_CODE_ASSERT_INTB 0x21 +#define PCI_MSG_CODE_ASSERT_INTC 0x22 +#define PCI_MSG_CODE_ASSERT_INTD 0x23 +#define PCI_MSG_CODE_DEASSERT_INTA 0x24 +#define PCI_MSG_CODE_DEASSERT_INTB 0x25 +#define PCI_MSG_CODE_DEASSERT_INTC 0x26 +#define PCI_MSG_CODE_DEASSERT_INTD 0x27 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump;