From patchwork Mon Aug 28 04:14:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 13367516 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 393B4C83F15 for ; Mon, 28 Aug 2023 04:15:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229927AbjH1EPM (ORCPT ); Mon, 28 Aug 2023 00:15:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229899AbjH1EOp (ORCPT ); Mon, 28 Aug 2023 00:14:45 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3FDE9129 for ; Sun, 27 Aug 2023 21:14:41 -0700 (PDT) X-IronPort-AV: E=Sophos;i="6.02,206,1688396400"; d="scan'208";a="177866556" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Aug 2023 13:14:40 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 699C2400446B; Mon, 28 Aug 2023 13:14:40 +0900 (JST) From: Yoshihiro Shimoda To: geert+renesas@glider.be, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Date: Mon, 28 Aug 2023 13:14:34 +0900 Message-Id: <20230828041434.2747699-3-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230828041434.2747699-1-yoshihiro.shimoda.uh@renesas.com> References: <20230828041434.2747699-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Enable PCIe Host controller channel 0 on R-Car S4-8 Spider board. Since this board has an Oculink connector, CLKREQ# pin of PFC for PCIe should not be used. So, using a GPIO is used to output the clock instead. Otherwise the controller cannot detect a PCIe device. Signed-off-by: Yoshihiro Shimoda --- .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 76a94812875e..48fb79aac32f 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -53,6 +53,12 @@ memory@480000000 { reg = <0x4 0x80000000 0x0 0x80000000>; }; + rc21012_pci: clk-rc21012-pci { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; + rc21012_ufs: clk-rc21012-ufs { compatible = "fixed-clock"; clock-frequency = <38400000>; @@ -106,6 +112,12 @@ gpio_exp_20: gpio@20 { reg = <0x20>; gpio-controller; #gpio-cells = <2>; + + rc21012-gpio2-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-high; + }; }; }; @@ -145,6 +157,11 @@ &mmc0 { status = "okay"; }; +&pciec0 { + reset-gpio = <&gpio_exp_20 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; @@ -202,6 +219,13 @@ &ufs { status = "okay"; }; +&pcie0_clkref { + compatible = "gpio-gate-clock"; + clocks = <&rc21012_pci>; + enable-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + /delete-property/ clock-frequency; +}; + &ufs30_clk { compatible = "gpio-gate-clock"; clocks = <&rc21012_ufs>;