| Message ID | 20230901075932.105822-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Under Review |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Enable 4-bit tx support | expand |
On Fri, Sep 1, 2023 at 9:59 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Enable Renesas at25ql128a flash connected to QSPI0. Also disable > the node from rzfive-smarc-som as it is untested. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v2->v3: > * Dropped subnodes, as all pins use the same power-source value. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 97cdad2a12e2..e28c1e3d5315 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -179,6 +179,12 @@ eth1_pins: eth1 { <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */ }; + qspi0_pins: qspi0 { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3", + "QSPI0_SPCLK", "QSPI0_SSL"; + power-source = <1800>; + }; + sdhi0_emmc_pins: sd0emmc { sd0_emmc_data { pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", @@ -230,6 +236,38 @@ sd0_mux_uhs { }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + spi-cpol; + spi-cpha; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x200000>; + read-only; + }; + user@200000 { + reg = <0x200000 0xE00000>; + }; + }; + }; +}; + #if (SW_SW0_DEV_SEL) &sdhi0 { pinctrl-0 = <&sdhi0_emmc_pins>; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi index c62debc7ca7e..0c9d72c32879 100644 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -42,6 +42,10 @@ phy1: ethernet-phy@7 { }; }; +&sbc { + status = "disabled"; +}; + &sdhi0 { status = "disabled"; };
Enable Renesas at25ql128a flash connected to QSPI0. Also disable the node from rzfive-smarc-som as it is untested. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v2->v3: * Dropped subnodes, as all pins use the same power-source value. v1->v2: * Enabled 4-bit tx support --- .../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 38 +++++++++++++++++++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 4 ++ 2 files changed, 42 insertions(+)