| Message ID | 20231023102223.1309614-5-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | irqchip/renesas-rzg2l: add support for RZ/G3S SoC | expand |
On Mon, Oct 23 2023 at 13:22, Claudiu wrote: > In hardware manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf) This filename is completely useless. > is available the following statement with regards to clearing > interrupts The RZ/G2L manual describes the operation to clear interrupts > though ISCR register: through the ISCR ... > > [Write operation] > When "Falling-edge detection", "Rising-edge detection" or > "Falling/Rising-edge detection" is set in ISCR.: > - In case ISTAT is 1 > 0: IRQn interrupt detection status is cleared. > 1: Invalid to write. > - In case ISTAT is 0 > Invalid to write. > When “Low-level detection” is set in IITSR.: > Invalid to write. > > Thus, take into account interrupt type when clearing interrupts though take the interrupt type into account... through the ISCR ... > ISCR register. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c > index 9ce0d6d67486..1ed9cb7178fa 100644 > --- a/drivers/irqchip/irq-renesas-rzg2l.c > +++ b/drivers/irqchip/irq-renesas-rzg2l.c > @@ -73,11 +73,17 @@ static void rzg2l_irq_eoi(struct irq_data *d) > unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; > struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); > u32 bit = BIT(hw_irq); > - u32 reg; > + u32 iitsr, iscr; > > - reg = readl_relaxed(priv->base + ISCR); > - if (reg & bit) > - writel_relaxed(reg & ~bit, priv->base + ISCR); > + iscr = readl_relaxed(priv->base + ISCR); > + iitsr = readl_relaxed(priv->base + IITSR); > + > + /* > + * ISCR could be cleared only if type is falling-edge, rising-edge or ISCR can only be cleared if the type is ... > + * falling/rising-edge. > + */ > + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) > + writel_relaxed(iscr & ~bit, priv->base + ISCR); > } > > static void rzg2l_tint_eoi(struct irq_data *d)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 9ce0d6d67486..1ed9cb7178fa 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -73,11 +73,17 @@ static void rzg2l_irq_eoi(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 bit = BIT(hw_irq); - u32 reg; + u32 iitsr, iscr; - reg = readl_relaxed(priv->base + ISCR); - if (reg & bit) - writel_relaxed(reg & ~bit, priv->base + ISCR); + iscr = readl_relaxed(priv->base + ISCR); + iitsr = readl_relaxed(priv->base + IITSR); + + /* + * ISCR could be cleared only if type is falling-edge, rising-edge or + * falling/rising-edge. + */ + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) + writel_relaxed(iscr & ~bit, priv->base + ISCR); } static void rzg2l_tint_eoi(struct irq_data *d)