| Message ID | 20231122121235.827122-12-peterlin@andestech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Support Andes PMU extension | expand |
On Wed, Nov 22, 2023 at 8:17 PM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > > xtheadpmu stands for T-Head Performance Monitor Unit extension. > Based on the added T-Head PMU ISA string, the SBI PMU driver > will make use of the non-standard irq source. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > --- > Changes v2 -> v3: > - New patch > Changes v3 -> v4: > - No change > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 64c3c2e6cbe0..7dcba86cfdd0 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -27,7 +27,7 @@ cpu0: cpu@0 { > riscv,isa = "rv64imafdc"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > - "zifencei", "zihpm"; > + "zifencei", "zihpm", "xtheadpmu"; Reviewed-by: Guo Ren <guoren@kernel.org> > #cooling-cells = <2>; > > cpu0_intc: interrupt-controller { > -- > 2.34.1 >
On Wed, Nov 22, 2023 at 08:12:33PM +0800, Yu Chien Peter Lin wrote: > xtheadpmu stands for T-Head Performance Monitor Unit extension. > Based on the added T-Head PMU ISA string, the SBI PMU driver > will make use of the non-standard irq source. Allwinner aren't the only ones using T-Head CPUs that the previous m*id pmu detection code would have matched on. I think the first three files below will also need to be updated: rg -l "thead,c[0-9]*\b[^-]" arch/riscv/boot/dts/ arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi arch/riscv/boot/dts/sophgo/cv1800b.dtsi arch/riscv/boot/dts/thead/th1520.dtsi arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi Cheers, Conor.
Hi Conor, On Thu, Nov 23, 2023 at 02:58:55PM +0000, Conor Dooley wrote: > On Wed, Nov 22, 2023 at 08:12:33PM +0800, Yu Chien Peter Lin wrote: > > xtheadpmu stands for T-Head Performance Monitor Unit extension. > > Based on the added T-Head PMU ISA string, the SBI PMU driver > > will make use of the non-standard irq source. > > Allwinner aren't the only ones using T-Head CPUs that the previous > m*id pmu detection code would have matched on. I think the first three > files below will also need to be updated: > > rg -l "thead,c[0-9]*\b[^-]" arch/riscv/boot/dts/ > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > arch/riscv/boot/dts/sophgo/cv1800b.dtsi > arch/riscv/boot/dts/thead/th1520.dtsi > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi That's really helpful, I'll add these .dtsi files in the patchset v5. Thanks, Peter Lin > Cheers, > Conor.
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..7dcba86cfdd0 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,7 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; #cooling-cells = <2>; cpu0_intc: interrupt-controller {
xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> --- Changes v2 -> v3: - New patch Changes v3 -> v4: - No change --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)