| Message ID | 20231122142310.203169-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Versa3 clock driver enhancements | expand |
Quoting Biju Das (2023-11-22 06:23:06) > Update vc3_get_div() to avoid divide by zero operation on > vc3_div_round_rate() by returning1, if there is no table match > found. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- Applied to clk-next
diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c index 00930d7bca77..3aad69a08512 100644 --- a/drivers/clk/clk-versaclock3.c +++ b/drivers/clk/clk-versaclock3.c @@ -477,7 +477,7 @@ static unsigned int vc3_get_div(const struct clk_div_table *table, if (clkt->val == val) return clkt->div; - return 0; + return 1; } static unsigned long vc3_div_recalc_rate(struct clk_hw *hw,
Update vc3_get_div() to avoid divide by zero operation on vc3_div_round_rate() by returning1, if there is no table match found. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/clk-versaclock3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)