From patchwork Tue Nov 28 08:04:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13470590 X-Patchwork-Delegate: geert@linux-m68k.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="QnXBzJ+g" Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC2FBC5 for ; Tue, 28 Nov 2023 00:04:47 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-507a29c7eefso6682828e87.1 for ; Tue, 28 Nov 2023 00:04:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1701158686; x=1701763486; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IoaNebWj6WdqROHUgOaXFN9XZbA5N7Tmp23rLr1Pw/A=; b=QnXBzJ+g115eGwqrZGkYam4RQe2aCxxcfRRj2P+wZuoHuDS+QUdWc3XIIS6xY6ygkX 9oLkZHXsXjJV+8eUvT/l1bQ3faYTQ0fdIBu7T94qOMwB0Nzp2T5utMqZCR6t5IyI9IHG g967U2liIckFIWnLJa7IFW7Z5vdDRLmSnex2U+y9fWrqKilyFH/2AYuVKZ8y6nXEu2YV iMlL5VRDuIB3pB65bSVEhfat1nNB7J+CNd0ZQuGtjvvjDSIdmJnCkGUQGIrAK7S6cieo XBUaMvD8HmKWHTWT2arr1E3aBf+lrQOqNFuDBwH5jrsemVtb/rn/EVI+I0Nwc5QiYnib R54w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701158686; x=1701763486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IoaNebWj6WdqROHUgOaXFN9XZbA5N7Tmp23rLr1Pw/A=; b=KXhCDfmNoZJzGcG0LFH5houH9KkucQbpsOjX1C6a0ijdwKvKC8lutwfy0VvYQZdh9g da6RqCbwpSg0xOJ5vn4LTYGhciNf7ORin8g8BisgmxzMRHZV3rSTw4S3GzQ0rYQpeAoJ wxLUtWPtSzqr7eFQape2pSZEAeSXGYGC3U0Y7sdzVV4tWbrdx5XXJU+1dRd72fmYciMa REUaHHrTX9AsGgognpSoVcZHtOKUWzisFPXjL2jizGDDjwywjHhS8Ds3jE1MUdxPwf1s 5ca04V628aFeXqHUfNWZCW252u1Ds8RipBEjr4WHr81KjYgM7riptzBoh3MWnIyHUzP1 DDiQ== X-Gm-Message-State: AOJu0Yzhn4YWehY1cKFoOvqpB+YWkkiziryav25SDABJqHNqkiiEean0 vCKEV6t8bFiphABRIleyRjnn7Q== X-Google-Smtp-Source: AGHT+IErqR2Cn2h+EP/BDSG5BWoEdhxj1fOVQMKlNR2IEscd0xHw7EMwldO6e4QfLqwg+Dyq/nh+Gw== X-Received: by 2002:a19:8c5c:0:b0:50a:b9dd:43f with SMTP id i28-20020a198c5c000000b0050ab9dd043fmr8382999lfj.21.1701158686229; Tue, 28 Nov 2023 00:04:46 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.125]) by smtp.gmail.com with ESMTPSA id g18-20020a05600c4ed200b0040b4ccdcffbsm1127534wmq.2.2023.11.28.00.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 00:04:45 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, richardcochran@gmail.com, p.zabel@pengutronix.de, yoshihiro.shimoda.uh@renesas.com, renesas@sang-engineering.com, robh@kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, mitsuhiro.kimura.kc@renesas.com, masaru.nagai.vx@renesas.com Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] net: ravb: Make write access to CXR35 first before accessing other EMAC registers Date: Tue, 28 Nov 2023 10:04:36 +0200 Message-Id: <20231128080439.852467-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231128080439.852467-1-claudiu.beznea.uj@bp.renesas.com> References: <20231128080439.852467-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Hardware manual of RZ/G3S (and RZ/G2L) specifies the following on the description of CXR35 register (chapter "PHY interface select register (CXR35)"): "After release reset, make write-access to this register before making write-access to other registers (except MDIOMOD). Even if not need to change the value of this register, make write-access to this register at least one time. Because RGMII/MII MODE is recognized by accessing this register". The setup procedure for EMAC module (chapter "Setup procedure" of RZ/G3S, RZ/G2L manuals) specifies the E-MAC.CXR35 register is the first EMAC register that is to be configured. Note [A] from chapter "PHY interface select register (CXR35)" specifies the following: [A] The case which CXR35 SEL_XMII is used for the selection of RGMII/MII in APB Clock 100 MHz. (1) To use RGMII interface, Set ‘H’03E8_0000’ to this register. (2) To use MII interface, Set ‘H’03E8_0002’ to this register. Take into account these indication. Fixes: 1089877ada8d ("ravb: Add RZ/G2L MII interface support") Reviewed-by: Sergey Shtylyov Signed-off-by: Claudiu Beznea --- Changes in v2: - none Changes since [1]: - collected Rb tag [1] https://lore.kernel.org/all/20231120084606.4083194-1-claudiu.beznea.uj@bp.renesas.com/ drivers/net/ethernet/renesas/ravb_main.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 0af2ace286be..62a986b5de41 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -515,6 +515,15 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); + if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { + ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); + } else { + ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, + CXR31_SEL_LINK0); + } + /* Receive frame limit set register */ ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); @@ -537,14 +546,6 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) /* E-MAC interrupt enable register */ ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); - - if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { - ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); - ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); - } else { - ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, - CXR31_SEL_LINK0); - } } static void ravb_emac_init_rcar(struct net_device *ndev)