| Message ID | 20240129151618.90922-3-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add IAX45 support for RZ/Five SoC | expand |
Hi Prabhakar, On Mon, Jan 29, 2024 at 4:16 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared > to the RZ/G2L (family) SoC. > > Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC > controller driver. Two new registers, IMSK and TMSK, are defined to > handle masking on RZ/Five SoC. The implementation utilizes a new data > structure, `struct rzg2l_irqc_data`, to determine mask support for a > specific controller instance. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/drivers/irqchip/irq-renesas-rzg2l.c > +++ b/drivers/irqchip/irq-renesas-rzg2l.c > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache { > u32 titsr[2]; > }; > > +/** > + * struct rzg2l_irqc_data - OF data structure > + * @mask_supported: Indicates if mask registers are available > + */ > +struct rzg2l_irqc_data { This structure has the same name as the single static struct rzg2l_irqc_priv instance, which is confusing. > + bool mask_supported; > +}; > + > /** > * struct rzg2l_irqc_priv - IRQ controller private data structure > * @base: Controller's base address > + * @data: OF data pointer > * @fwspec: IRQ firmware specific data > * @lock: Lock to serialize access to hardware registers > * @cache: Registers cache for suspend/resume > */ > static struct rzg2l_irqc_priv { > void __iomem *base; > + const struct rzg2l_irqc_data *data; Replacing this by a bool would avoid a pointer dereference in each user, and allows you to make rzg2l_irqc_data etc. __initconst. > struct irq_fwspec fwspec[IRQC_NUM_IRQ]; > raw_spinlock_t lock; > struct rzg2l_irqc_reg_cache cache; > @@ -371,9 +475,23 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, > return 0; > } > > +static const struct rzg2l_irqc_data rzfive_irqc_data = { > + .mask_supported = true, > +}; > + > +static const struct rzg2l_irqc_data rzg2l_irqc_default_data = { > + .mask_supported = false, > +}; > + > +static const struct of_device_id rzg2l_irqc_matches[] = { > + { .compatible = "renesas,r9a07g043f-irqc", .data = &rzfive_irqc_data }, > + { } > +}; > + > static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) > { > struct irq_domain *irq_domain, *parent_domain; > + const struct of_device_id *match; > struct platform_device *pdev; > struct reset_control *resetn; > int ret; > @@ -392,6 +510,12 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) > if (!rzg2l_irqc_data) > return -ENOMEM; > > + match = of_match_node(rzg2l_irqc_matches, node); > + if (match) > + rzg2l_irqc_data->data = match->data; > + else > + rzg2l_irqc_data->data = &rzg2l_irqc_default_data; Instead of matching a second time, I'd rather add a second IRQCHIP_MATCH() entry with a different init function, passing the actual rzg2l_irqc_data pointer. > + > rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); > if (IS_ERR(rzg2l_irqc_data->base)) > return PTR_ERR(rzg2l_irqc_data->base); Gr{oetje,eeting}s, Geert
Hi Geert, Thank you for the review. On Tue, Jan 30, 2024 at 11:38 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Jan 29, 2024 at 4:16 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared > > to the RZ/G2L (family) SoC. > > > > Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC > > controller driver. Two new registers, IMSK and TMSK, are defined to > > handle masking on RZ/Five SoC. The implementation utilizes a new data > > structure, `struct rzg2l_irqc_data`, to determine mask support for a > > specific controller instance. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/drivers/irqchip/irq-renesas-rzg2l.c > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache { > > u32 titsr[2]; > > }; > > > > +/** > > + * struct rzg2l_irqc_data - OF data structure > > + * @mask_supported: Indicates if mask registers are available > > + */ > > +struct rzg2l_irqc_data { > > This structure has the same name as the single static struct > rzg2l_irqc_priv instance, which is confusing. > Agreed, I will rename it to rzg2l_irqc_of_data > > + bool mask_supported; > > +}; > > + > > /** > > * struct rzg2l_irqc_priv - IRQ controller private data structure > > * @base: Controller's base address > > + * @data: OF data pointer > > * @fwspec: IRQ firmware specific data > > * @lock: Lock to serialize access to hardware registers > > * @cache: Registers cache for suspend/resume > > */ > > static struct rzg2l_irqc_priv { > > void __iomem *base; > > + const struct rzg2l_irqc_data *data; > > Replacing this by a bool would avoid a pointer dereference in each user, > and allows you to make rzg2l_irqc_data etc. __initconst. > Do you mean just add "bool mask_supported" here and get rid of struct rzg2l_irqc_data ? Can you please elaborate here.. > > struct irq_fwspec fwspec[IRQC_NUM_IRQ]; > > raw_spinlock_t lock; > > struct rzg2l_irqc_reg_cache cache; > > > @@ -371,9 +475,23 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, > > return 0; > > } > > > > +static const struct rzg2l_irqc_data rzfive_irqc_data = { > > + .mask_supported = true, > > +}; > > + > > +static const struct rzg2l_irqc_data rzg2l_irqc_default_data = { > > + .mask_supported = false, > > +}; > > + > > +static const struct of_device_id rzg2l_irqc_matches[] = { > > + { .compatible = "renesas,r9a07g043f-irqc", .data = &rzfive_irqc_data }, > > + { } > > +}; > > + > > static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) > > { > > struct irq_domain *irq_domain, *parent_domain; > > + const struct of_device_id *match; > > struct platform_device *pdev; > > struct reset_control *resetn; > > int ret; > > @@ -392,6 +510,12 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) > > if (!rzg2l_irqc_data) > > return -ENOMEM; > > > > + match = of_match_node(rzg2l_irqc_matches, node); > > + if (match) > > + rzg2l_irqc_data->data = match->data; > > + else > > + rzg2l_irqc_data->data = &rzg2l_irqc_default_data; > > Instead of matching a second time, I'd rather add a second > IRQCHIP_MATCH() entry with a different init function, passing the > actual rzg2l_irqc_data pointer. > OK, or rather just pass true/false instead of rzg2l_irqc_of_data pointer.? Cheers, Prabhakar
Hi Prabhakar, On Wed, Jan 31, 2024 at 7:36 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Tue, Jan 30, 2024 at 11:38 AM Geert Uytterhoeven > <geert@linux-m68k.org> wrote: > > On Mon, Jan 29, 2024 at 4:16 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared > > > to the RZ/G2L (family) SoC. > > > > > > Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC > > > controller driver. Two new registers, IMSK and TMSK, are defined to > > > handle masking on RZ/Five SoC. The implementation utilizes a new data > > > structure, `struct rzg2l_irqc_data`, to determine mask support for a > > > specific controller instance. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > --- a/drivers/irqchip/irq-renesas-rzg2l.c > > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c > > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache { > > > u32 titsr[2]; > > > }; > > > > > > +/** > > > + * struct rzg2l_irqc_data - OF data structure > > > + * @mask_supported: Indicates if mask registers are available > > > + */ > > > +struct rzg2l_irqc_data { > > > > This structure has the same name as the single static struct > > rzg2l_irqc_priv instance, which is confusing. > > > Agreed, I will rename it to rzg2l_irqc_of_data > > > > + bool mask_supported; > > > +}; > > > + > > > /** > > > * struct rzg2l_irqc_priv - IRQ controller private data structure > > > * @base: Controller's base address > > > + * @data: OF data pointer > > > * @fwspec: IRQ firmware specific data > > > * @lock: Lock to serialize access to hardware registers > > > * @cache: Registers cache for suspend/resume > > > */ > > > static struct rzg2l_irqc_priv { > > > void __iomem *base; > > > + const struct rzg2l_irqc_data *data; > > > > Replacing this by a bool would avoid a pointer dereference in each user, > > and allows you to make rzg2l_irqc_data etc. __initconst. > > > Do you mean just add "bool mask_supported" here and get rid of struct > rzg2l_irqc_data ? Can you please elaborate here.. Either add "bool mask_supported" here, or add a copy of the full struct rzg2l_irqc_data (see below). > > > > struct irq_fwspec fwspec[IRQC_NUM_IRQ]; > > > raw_spinlock_t lock; > > > struct rzg2l_irqc_reg_cache cache; > > > > > @@ -371,9 +475,23 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, > > > return 0; > > > } > > > > > > +static const struct rzg2l_irqc_data rzfive_irqc_data = { > > > + .mask_supported = true, > > > +}; > > > + > > > +static const struct rzg2l_irqc_data rzg2l_irqc_default_data = { > > > + .mask_supported = false, > > > +}; > > > + > > > +static const struct of_device_id rzg2l_irqc_matches[] = { > > > + { .compatible = "renesas,r9a07g043f-irqc", .data = &rzfive_irqc_data }, > > > + { } > > > +}; > > > + > > > static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) > > > { > > > struct irq_domain *irq_domain, *parent_domain; > > > + const struct of_device_id *match; > > > struct platform_device *pdev; > > > struct reset_control *resetn; > > > int ret; > > > @@ -392,6 +510,12 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) > > > if (!rzg2l_irqc_data) > > > return -ENOMEM; > > > > > > + match = of_match_node(rzg2l_irqc_matches, node); > > > + if (match) > > > + rzg2l_irqc_data->data = match->data; > > > + else > > > + rzg2l_irqc_data->data = &rzg2l_irqc_default_data; > > > > Instead of matching a second time, I'd rather add a second > > IRQCHIP_MATCH() entry with a different init function, passing the > > actual rzg2l_irqc_data pointer. > > > OK, or rather just pass true/false instead of rzg2l_irqc_of_data pointer.? Yes, that would be fine for me, too. It all depends on whether you plan to add, or see a need for adding, more flags or other fields in the future (and even for flags, you could combine them in an unsigned long). Gr{oetje,eeting}s, Geert
Hi Geert, On Thu, Feb 1, 2024 at 8:34 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Wed, Jan 31, 2024 at 7:36 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Tue, Jan 30, 2024 at 11:38 AM Geert Uytterhoeven > > <geert@linux-m68k.org> wrote: > > > On Mon, Jan 29, 2024 at 4:16 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared > > > > to the RZ/G2L (family) SoC. > > > > > > > > Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC > > > > controller driver. Two new registers, IMSK and TMSK, are defined to > > > > handle masking on RZ/Five SoC. The implementation utilizes a new data > > > > structure, `struct rzg2l_irqc_data`, to determine mask support for a > > > > specific controller instance. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > --- a/drivers/irqchip/irq-renesas-rzg2l.c > > > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c > > > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache { > > > > u32 titsr[2]; > > > > }; > > > > > > > > +/** > > > > + * struct rzg2l_irqc_data - OF data structure > > > > + * @mask_supported: Indicates if mask registers are available > > > > + */ > > > > +struct rzg2l_irqc_data { > > > > > > This structure has the same name as the single static struct > > > rzg2l_irqc_priv instance, which is confusing. > > > > > Agreed, I will rename it to rzg2l_irqc_of_data > > > > > > + bool mask_supported; > > > > +}; > > > > + > > > > /** > > > > * struct rzg2l_irqc_priv - IRQ controller private data structure > > > > * @base: Controller's base address > > > > + * @data: OF data pointer > > > > * @fwspec: IRQ firmware specific data > > > > * @lock: Lock to serialize access to hardware registers > > > > * @cache: Registers cache for suspend/resume > > > > */ > > > > static struct rzg2l_irqc_priv { > > > > void __iomem *base; > > > > + const struct rzg2l_irqc_data *data; > > > > > > Replacing this by a bool would avoid a pointer dereference in each user, > > > and allows you to make rzg2l_irqc_data etc. __initconst. > > > > > Do you mean just add "bool mask_supported" here and get rid of struct > > rzg2l_irqc_data ? Can you please elaborate here.. > > Either add "bool mask_supported" here, or add a copy of the full > struct rzg2l_irqc_data (see below). > OK, i'll keep a copy of struct rzg2l_irqc_data here... > > > > > > struct irq_fwspec fwspec[IRQC_NUM_IRQ]; > > > > raw_spinlock_t lock; > > > > struct rzg2l_irqc_reg_cache cache; > > > > > > > @@ -371,9 +475,23 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, > > > > return 0; > > > > } > > > > > > > > +static const struct rzg2l_irqc_data rzfive_irqc_data = { > > > > + .mask_supported = true, > > > > +}; > > > > + > > > > +static const struct rzg2l_irqc_data rzg2l_irqc_default_data = { > > > > + .mask_supported = false, > > > > +}; > > > > + > > > > +static const struct of_device_id rzg2l_irqc_matches[] = { > > > > + { .compatible = "renesas,r9a07g043f-irqc", .data = &rzfive_irqc_data }, > > > > + { } > > > > +}; > > > > + > > > > static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) > > > > { > > > > struct irq_domain *irq_domain, *parent_domain; > > > > + const struct of_device_id *match; > > > > struct platform_device *pdev; > > > > struct reset_control *resetn; > > > > int ret; > > > > @@ -392,6 +510,12 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) > > > > if (!rzg2l_irqc_data) > > > > return -ENOMEM; > > > > > > > > + match = of_match_node(rzg2l_irqc_matches, node); > > > > + if (match) > > > > + rzg2l_irqc_data->data = match->data; > > > > + else > > > > + rzg2l_irqc_data->data = &rzg2l_irqc_default_data; > > > > > > Instead of matching a second time, I'd rather add a second > > > IRQCHIP_MATCH() entry with a different init function, passing the > > > actual rzg2l_irqc_data pointer. > > > > > OK, or rather just pass true/false instead of rzg2l_irqc_of_data pointer.? > > Yes, that would be fine for me, too. > It all depends on whether you plan to add, or see a need for adding, > more flags or other fields in the future (and even for flags, you could > combine them in an unsigned long). > I'll keep the bool flag for now and update it as and when it grows. I see future SoCs with a lot of other interrupts being supported by this block. Cheers, Prabhakar > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 9494fc26259c..949280f95c29 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -37,6 +37,8 @@ #define TSSEL_SHIFT(n) (8 * (n)) #define TSSEL_MASK GENMASK(7, 0) #define IRQ_MASK 0x3 +#define IMSK 0x10010 +#define TMSK 0x10020 #define TSSR_OFFSET(n) ((n) % 4) #define TSSR_INDEX(n) ((n) / 4) @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache { u32 titsr[2]; }; +/** + * struct rzg2l_irqc_data - OF data structure + * @mask_supported: Indicates if mask registers are available + */ +struct rzg2l_irqc_data { + bool mask_supported; +}; + /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address + * @data: OF data pointer * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { void __iomem *base; + const struct rzg2l_irqc_data *data; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; raw_spinlock_t lock; struct rzg2l_irqc_reg_cache cache; @@ -129,44 +141,136 @@ static void rzg2l_irqc_eoi(struct irq_data *d) irq_chip_eoi_parent(d); } +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 imsk = readl_relaxed(priv->base + IMSK); + u32 bit = BIT(hwirq - IRQC_IRQ_START); + + writel_relaxed(imsk | bit, priv->base + IMSK); +} + +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 imsk = readl_relaxed(priv->base + IMSK); + u32 bit = BIT(hwirq - IRQC_IRQ_START); + + writel_relaxed(imsk & ~bit, priv->base + IMSK); +} + +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 tmsk = readl_relaxed(priv->base + TMSK); + u32 bit = BIT(hwirq - IRQC_TINT_START); + + writel_relaxed(tmsk | bit, priv->base + TMSK); +} + +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 tmsk = readl_relaxed(priv->base + TMSK); + u32 bit = BIT(hwirq - IRQC_TINT_START); + + writel_relaxed(tmsk & ~bit, priv->base + TMSK); +} + +/* Must be called while priv->lock is held */ +static void rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq) +{ + if (!priv->data->mask_supported) + return; + + if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT) + rzg2l_irqc_mask_irq_interrupt(priv, hwirq); + else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + rzg2l_irqc_mask_tint_interrupt(priv, hwirq); +} + +static void rzg2l_irqc_mask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + + raw_spin_lock(&priv->lock); + rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d)); + raw_spin_unlock(&priv->lock); + irq_chip_mask_parent(d); +} + +/* Must be called while priv->lock is held */ +static void rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq) +{ + if (!priv->data->mask_supported) + return; + + if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT) + rzg2l_irqc_unmask_irq_interrupt(priv, hwirq); + else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + rzg2l_irqc_unmask_tint_interrupt(priv, hwirq); +} + +static void rzg2l_irqc_unmask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + + raw_spin_lock(&priv->lock); + rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d)); + raw_spin_unlock(&priv->lock); + irq_chip_unmask_parent(d); +} + static void rzg2l_irqc_irq_disable(struct irq_data *d) { + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hw_irq = irqd_to_hwirq(d); if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 offset = hw_irq - IRQC_TINT_START; u32 tssr_offset = TSSR_OFFSET(offset); u8 tssr_index = TSSR_INDEX(offset); u32 reg; raw_spin_lock(&priv->lock); + rzg2l_irqc_mask_once(priv, hw_irq); reg = readl_relaxed(priv->base + TSSR(tssr_index)); reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); writel_relaxed(reg, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); + } else { + raw_spin_lock(&priv->lock); + rzg2l_irqc_mask_once(priv, hw_irq); + raw_spin_unlock(&priv->lock); } + irq_chip_disable_parent(d); } static void rzg2l_irqc_irq_enable(struct irq_data *d) { + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hw_irq = irqd_to_hwirq(d); if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d); - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 offset = hw_irq - IRQC_TINT_START; u32 tssr_offset = TSSR_OFFSET(offset); u8 tssr_index = TSSR_INDEX(offset); u32 reg; raw_spin_lock(&priv->lock); + rzg2l_irqc_unmask_once(priv, hw_irq); reg = readl_relaxed(priv->base + TSSR(tssr_index)); reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset); writel_relaxed(reg, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); + } else { + raw_spin_lock(&priv->lock); + rzg2l_irqc_unmask_once(priv, hw_irq); + raw_spin_unlock(&priv->lock); } + irq_chip_enable_parent(d); } @@ -294,8 +398,8 @@ static struct syscore_ops rzg2l_irqc_syscore_ops = { static const struct irq_chip irqc_chip = { .name = "rzg2l-irqc", .irq_eoi = rzg2l_irqc_eoi, - .irq_mask = irq_chip_mask_parent, - .irq_unmask = irq_chip_unmask_parent, + .irq_mask = rzg2l_irqc_mask, + .irq_unmask = rzg2l_irqc_unmask, .irq_disable = rzg2l_irqc_irq_disable, .irq_enable = rzg2l_irqc_irq_enable, .irq_get_irqchip_state = irq_chip_get_parent_state, @@ -371,9 +475,23 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, return 0; } +static const struct rzg2l_irqc_data rzfive_irqc_data = { + .mask_supported = true, +}; + +static const struct rzg2l_irqc_data rzg2l_irqc_default_data = { + .mask_supported = false, +}; + +static const struct of_device_id rzg2l_irqc_matches[] = { + { .compatible = "renesas,r9a07g043f-irqc", .data = &rzfive_irqc_data }, + { } +}; + static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) { struct irq_domain *irq_domain, *parent_domain; + const struct of_device_id *match; struct platform_device *pdev; struct reset_control *resetn; int ret; @@ -392,6 +510,12 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) if (!rzg2l_irqc_data) return -ENOMEM; + match = of_match_node(rzg2l_irqc_matches, node); + if (match) + rzg2l_irqc_data->data = match->data; + else + rzg2l_irqc_data->data = &rzg2l_irqc_default_data; + rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); if (IS_ERR(rzg2l_irqc_data->base)) return PTR_ERR(rzg2l_irqc_data->base);