From patchwork Thu Feb 8 23:24:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13550759 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6A8C655798; Thu, 8 Feb 2024 23:24:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707434695; cv=none; b=pXBq/SYe5hCEAlKqnKxH0hjseld4/svR0NA3DyjZYQhX2QQP/1q2f0xLSOlKn5l+fEhEnCMkxwrpiO9E9CmEx4OCihcGwZVeuR9/XsIgWp1s89Ollm6txL6kriyeWyYzhuUyd4bRUi0266e/MH4tkf8GDh/wFcE3M1szhUEoXxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707434695; c=relaxed/simple; bh=svvyA2OoPQBEnjShQYCWi04NK7mkxjERO0s6YZk0HkM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nLKaXQ3Wp785pkKfZ2CFj2siQ9Cfs0HmBsOxGn1/9LKJvoiGgpIkKw1PI/ks+T2AoMm1uD3cuMvYsMWCiJLCCZObRT6IyZjcoNWi27SXbGLPy1+MFX6b8/ETpTlx/oCXVAstzVAZ5TEQzrlvf+M9sW/dGZtnBeEYs2I28Y587Fg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-IronPort-AV: E=Sophos;i="6.05,255,1701097200"; d="scan'208";a="197291926" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 09 Feb 2024 08:24:52 +0900 Received: from mulinux.home (unknown [10.226.92.227]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1E00E4009BDC; Fri, 9 Feb 2024 08:24:47 +0900 (JST) From: Fabrizio Castro To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven Cc: Biju Das , Magnus Damm , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Krzysztof Kozlowski Subject: [PATCH v6 1/4] dt-bindings: pwm: Add RZ/V2M PWM binding Date: Thu, 8 Feb 2024 23:24:08 +0000 Message-Id: <20240208232411.316936-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208232411.316936-1-fabrizio.castro.jz@renesas.com> References: <20240208232411.316936-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Biju Das Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM). Signed-off-by: Biju Das Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v5->v6: * No change v4->v5: * No change v3->v4: * No change v2->v3: * Added Rb tag from Geert. v1->v2: * Added Rb tag from Krzysztof and the keep the Rb tag as the below * changes are trivial * Updated the description for APB clock * Added resets required property * Updated the example with resets property .../bindings/pwm/renesas,rzv2m-pwm.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml new file mode 100644 index 000000000000..ddeed7550923 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,rzv2m-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2{M, MA} PWM Timer (PWM) + +maintainers: + - Biju Das + +description: | + The RZ/V2{M, MA} PWM Timer (PWM) composed of 16 channels. It supports the + following functions + * The PWM has 24-bit counters which operate at PWM_CLK (48 MHz). + * The frequency division ratio for internal counter operation is selectable + as PWM_CLK divided by 1, 16, 256, or 2048. + * The period as well as the duty cycle is adjustable. + * The low-level and high-level order of the PWM signals can be inverted. + * The duty cycle of the PWM signal is selectable in the range from 0 to 100%. + * The minimum resolution is 20.83 ns. + * Three interrupt sources: Rising and falling edges of the PWM signal and + clearing of the counter + * Counter operation and the bus interface are asynchronous and both can + operate independently of the magnitude relationship of the respective + clock periods. + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwm # RZ/V2M + - renesas,r9a09g055-pwm # RZ/V2MA + - const: renesas,rzv2m-pwm + + reg: + maxItems: 1 + + '#pwm-cells': + const: 2 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: APB clock + - description: PWM clock + + clock-names: + items: + - const: apb + - const: pwm + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + +allOf: + - $ref: pwm.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + + pwm8: pwm@a4010400 { + compatible = "renesas,r9a09g011-pwm", "renesas,rzv2m-pwm"; + reg = <0xa4010400 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>, + <&cpg CPG_MOD R9A09G011_PWM8_CLK>; + clock-names = "apb", "pwm"; + power-domains = <&cpg>; + resets = <&cpg R9A09G011_PWM_GPF_PRESETN>; + #pwm-cells = <2>; + };