| Message ID | 20240222132117.137729-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 4b15a38590f66da7e238a919242b69a235a261ec |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Enable RZ/{G2L,G2LC} and RZ/V2L DU | expand |
On Thu, Feb 22, 2024 at 2:21 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add DU node to RZ/G2L SoC DTSI. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v8->v9: > * Added ports properties. > * Dropped Rb tag from Geert. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.9. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 66f68fc2b241..66b47812da9b 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -820,6 +820,33 @@ fcpvd: fcp@10880000 { resets = <&cpg R9A07G044_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g044-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>;
Add DU node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v8->v9: * Added ports properties. * Dropped Rb tag from Geert. v7->v8: * Added Rb tag from Geert. v7: * New patch. --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+)