| Message ID | 20240520075931.126476-3-yoshihiro.shimoda.uh@renesas.com (mailing list archive) |
|---|---|
| State | Under Review |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | arm64: dts: renesas: r8a779g0: add PCIe support | expand |
On Mon, May 20, 2024 at 9:59 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > Enable PCIe Host controller channel 0 on R-Car V4H White Hawk boards. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> My Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> on v1 is still valid. As this has a hard dependency on the driver changes, it must be postponed until the driver changes have landed upstream. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi index 8ac17370ff36..3fc9a541f777 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi @@ -111,6 +111,12 @@ mini_dp_con_in: endpoint { }; }; + pcie_clk: clk-9fgv0841-pci { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; + reg_1p2v: regulator-1p2v { compatible = "regulator-fixed"; regulator-name = "fixed-1.2V"; @@ -277,6 +283,18 @@ &mmc0 { status = "okay"; }; +&pcie0_clkref { + compatible = "gpio-gate-clock"; + clocks = <&pcie_clk>; + enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + /delete-property/ clock-frequency; +}; + +&pciec0 { + reset-gpio = <&io_expander_a 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default";
Enable PCIe Host controller channel 0 on R-Car V4H White Hawk boards. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- .../dts/renesas/white-hawk-cpu-common.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)