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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286eef9eesm87272555e9.9.2024.06.14.00.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 00:19:50 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 01/12] clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP Date: Fri, 14 Jun 2024 10:19:21 +0300 Message-Id: <20240614071932.1014067-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB) that generates the RTC clock. Add clock, reset and power domain support for it. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a08g045-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index b068733b145f..2ae97c29c377 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -215,6 +215,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), + DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; static const struct rzg2l_reset r9a08g045_resets[] = { @@ -231,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), + DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { @@ -238,6 +240,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_IA55_PCLK, MOD_CLK_BASE + R9A08G045_IA55_CLK, MOD_CLK_BASE + R9A08G045_DMAC_ACLK, + MOD_CLK_BASE + R9A08G045_VBAT_BCLK, }; static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { @@ -275,6 +278,9 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { DEF_PD("scif0", R9A08G045_PD_SCIF0, DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), RZG2L_PD_F_NONE), + DEF_PD("vbat", R9A08G045_PD_VBAT, + DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), + RZG2L_PD_F_ALWAYS_ON), }; const struct rzg2l_cpg_info r9a08g045_cpg_info = {