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AJvYcCU31yX+zVJsjnQd6BKBcYFf2zZOzzA8k1LJAJhJHR/hrfM+FY/XHixagwY+EO6S9cgIt5b0/L4QtmFb/nKCanicju+WqwbuMX96q2MhsnhCc9NPfIs0bQi5LNSz0mgJx99+ZSSCdv+s7w== X-Gm-Message-State: AOJu0YxC8ypBymHgHGe4+G2dfYFkq/9F61IPZYhvv9U3DQ1m3Kc4OWr7 i7fWOW8ZwJdSCtMdxLfcL+OV5Rz40JgkAuZylAT7lJ9Kem2bKoxh X-Google-Smtp-Source: AGHT+IFU2BQNoe5ElKYcuGGZUhS+jx5+G1VSSadIGz9IqSPchK6rXimY4Od4/Mp6yqGMkMjGahQwmA== X-Received: by 2002:a05:6000:248:b0:363:337a:3e0 with SMTP id ffacd0b85a97d-363338946b5mr8521f8f.1.1718732932393; Tue, 18 Jun 2024 10:48:52 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:d6f0:b448:a40c:81a7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36289a4faeasm1253644f8f.95.2024.06.18.10.48.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:48:51 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/4] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide Date: Tue, 18 Jun 2024 18:48:28 +0100 Message-Id: <20240618174831.415583-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Modify the `PIN_CFG_MASK()` macro to be 32-bit wide. The current maximum value for `PIN_CFG_*` is `BIT(21)`, which fits within a 32-bit mask. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 32945d4c8dc0..bfaeeb00ac4a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -89,7 +89,7 @@ #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55) #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47) -#define PIN_CFG_MASK GENMASK_ULL(46, 0) +#define PIN_CFG_MASK GENMASK_ULL(31, 0) /* * m indicates the bitmap of supported pins, a is the register index @@ -1187,7 +1187,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, u64 *pin_data = pin->drv_data; unsigned int arg = 0; u32 off; - u64 cfg; + u32 cfg; int ret; u8 bit; @@ -1322,7 +1322,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, u64 *pin_data = pin->drv_data; unsigned int i, arg, index; u32 off, param; - u64 cfg; + u32 cfg; int ret; u8 bit; @@ -2755,9 +2755,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen for (u32 port = 0; port < nports; port++) { bool has_iolh, has_ien; - u64 cfg, caps; + u32 off, caps; u8 pincnt; - u32 off; + u64 cfg; cfg = pctrl->data->port_pin_configs[port]; off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); @@ -2801,7 +2801,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) { struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; - u64 caps; + u32 caps; u32 i; /*