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AJvYcCWV4UjWqxTbRonqb0mnzQMzhpE/GyHUgWlxg17NQnQAK4ruw1LhBNTslxWw+szoT6qclh7/bxexZsOxLYLeez9C0by6R3Um+I9ARnHx75o6AuObwxZT/A3Yclp3U1HZ6R7CsCOLR6NOzg== X-Gm-Message-State: AOJu0YzphymGB/z4eABUjAoJxltg09FQ7MEIKOnlvfo/PCrtlMR4eUPy vcvmOdp5jdQvm0cJCg56CphDOa8boFsjo3Xvuv3HasKMtgvFMhMn X-Google-Smtp-Source: AGHT+IFHQW6hBw0alUqJPTFyqp+/+k7A7etWQ3YmnqQjExIuzCXz4LWsbihlWLkKn7jeoQ5RpYx+OA== X-Received: by 2002:a5d:4009:0:b0:362:5f91:901a with SMTP id ffacd0b85a97d-3625f91a24amr1749782f8f.31.1718732934380; Tue, 18 Jun 2024 10:48:54 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:d6f0:b448:a40c:81a7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36289a4faeasm1253644f8f.95.2024.06.18.10.48.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:48:53 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/4] pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file Date: Tue, 18 Jun 2024 18:48:30 +0100 Message-Id: <20240618174831.415583-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Define `RZG2L_SINGLE_PIN` at the top of the file to clarify its use for dedicated pins for improved readability. While at it update the comment for `RZG2L_SINGLE_PIN_PACK` macro and place it just above the macro for clarity. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index b79dd1ea2616..37a99d33400d 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -64,6 +64,8 @@ #define PIN_CFG_ELC BIT(20) #define PIN_CFG_IOLH_RZV2H BIT(21) +#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ + #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ PIN_CFG_PUPD | \ @@ -105,15 +107,13 @@ */ #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) -/* - * BIT(63) indicates dedicated pin, p is the register index while - * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits - * (b * 8) and f is the pin configuration capabilities supported. - */ -#define RZG2L_SINGLE_PIN BIT_ULL(63) #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56) #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53) - +/* + * p is the register index while referencing to SR/IEN/IOLH/FILxx + * registers, b is the register bits (b * 8) and f is the pin + * configuration capabilities supported. + */ #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \