diff mbox series

[1/4] clk: renesas: rzg2l-cpg: Use devres API to register clocks

Message ID 20240628131021.177866-2-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series clk: renesas: rzg2l-cpg: Refactor and simplify clock registration | expand

Commit Message

Lad, Prabhakar June 28, 2024, 1:10 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

We are using devres APIs for divider, mux and pll5 clocks so for
consistency use the devres APIs for module and PLL clocks.

While at it switched to clk_hw_register() instead of clk_register()
as this has been marked as deprecated interface.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/rzg2l-cpg.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

Comments

Geert Uytterhoeven July 12, 2024, 1:54 p.m. UTC | #1 
Hi Prabhakar,

On Fri, Jun 28, 2024 at 3:11 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> We are using devres APIs for divider, mux and pll5 clocks so for
> consistency use the devres APIs for module and PLL clocks.
>
> While at it switched to clk_hw_register() instead of clk_register()
> as this has been marked as deprecated interface.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -1023,6 +1023,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
>         struct clk_init_data init;
>         const char *parent_name;
>         struct pll_clk *pll_clk;
> +       int ret;
>
>         parent = clks[core->parent & 0xffff];
>         if (IS_ERR(parent))
> @@ -1045,7 +1046,11 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
>         pll_clk->priv = priv;
>         pll_clk->type = core->type;
>
> -       return clk_register(NULL, &pll_clk->hw);
> +       ret = devm_clk_hw_register(dev, &pll_clk->hw);
> +       if (ret)
> +               return NULL;

rzg2l_cpg_pll_clk_register() can return an ERR_PTR, so please
propagate the error code.

> +
> +       return pll_clk->hw.clk;
>  }

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert
Lad, Prabhakar July 15, 2024, 10:10 a.m. UTC | #2 
Hi Geert,

Thank you for the review.

On Fri, Jul 12, 2024 at 2:55 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, Jun 28, 2024 at 3:11 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > We are using devres APIs for divider, mux and pll5 clocks so for
> > consistency use the devres APIs for module and PLL clocks.
> >
> > While at it switched to clk_hw_register() instead of clk_register()
> > as this has been marked as deprecated interface.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -1023,6 +1023,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
> >         struct clk_init_data init;
> >         const char *parent_name;
> >         struct pll_clk *pll_clk;
> > +       int ret;
> >
> >         parent = clks[core->parent & 0xffff];
> >         if (IS_ERR(parent))
> > @@ -1045,7 +1046,11 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
> >         pll_clk->priv = priv;
> >         pll_clk->type = core->type;
> >
> > -       return clk_register(NULL, &pll_clk->hw);
> > +       ret = devm_clk_hw_register(dev, &pll_clk->hw);
> > +       if (ret)
> > +               return NULL;
>
> rzg2l_cpg_pll_clk_register() can return an ERR_PTR, so please
> propagate the error code.
>
Ok, I'll propagate the error.

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 04b78064d4e0..91cf972a20c3 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1023,6 +1023,7 @@  rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
 	struct clk_init_data init;
 	const char *parent_name;
 	struct pll_clk *pll_clk;
+	int ret;
 
 	parent = clks[core->parent & 0xffff];
 	if (IS_ERR(parent))
@@ -1045,7 +1046,11 @@  rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
 	pll_clk->priv = priv;
 	pll_clk->type = core->type;
 
-	return clk_register(NULL, &pll_clk->hw);
+	ret = devm_clk_hw_register(dev, &pll_clk->hw);
+	if (ret)
+		return NULL;
+
+	return pll_clk->hw.clk;
 }
 
 static struct clk
@@ -1337,6 +1342,7 @@  rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
 	struct clk *parent, *clk;
 	const char *parent_name;
 	unsigned int i;
+	int ret;
 
 	WARN_DEBUG(id < priv->num_core_clks);
 	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
@@ -1380,10 +1386,11 @@  rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
 	clock->priv = priv;
 	clock->hw.init = &init;
 
-	clk = clk_register(NULL, &clock->hw);
-	if (IS_ERR(clk))
+	ret = devm_clk_hw_register(dev, &clock->hw);
+	if (ret)
 		goto fail;
 
+	clk = clock->hw.clk;
 	dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 	priv->clks[id] = clk;