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AJvYcCXEu64B8GooUciPRtHkmggjCt/axK68zW4sQ9gXk69WqeY++dXN2/nLEvaVXRY/UrXnQY3KQIbPe+jzcdDytQDUGskMlf7NKWIXjjQRPbjp9o5sWYZdKKbfR3gW19o3IcUtQHN9e7b38za5r5U= X-Gm-Message-State: AOJu0YxnSCKitNbNxaxJ+wXgpAdO4kcBHKce+C5r3IMxKOg4UYGnRNVw ANfRRSnwsuZm5gYrp5/bqIfWnKEO3bpnR8HQWq6bErYsl6Qpjnwf X-Google-Smtp-Source: AGHT+IEGeSQuONWoEpvbQiQ961s/N9yM9EjuTTYvt05lrZbT3+aX+xcRKPQjvBxYO6ZqnnkY9s41wA== X-Received: by 2002:a05:600c:2192:b0:424:bb45:cdea with SMTP id 5b1f17b1804b1-424bb45cedbmr58643135e9.22.1719580265593; Fri, 28 Jun 2024 06:11:05 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:2595:4364:d152:dff3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4256af557fesm35298865e9.11.2024.06.28.06.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 06:11:05 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/4] clk: renesas: rzg2l-cpg: Use devres API to register clocks Date: Fri, 28 Jun 2024 14:10:18 +0100 Message-Id: <20240628131021.177866-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628131021.177866-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240628131021.177866-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar We are using devres APIs for divider, mux and pll5 clocks so for consistency use the devres APIs for module and PLL clocks. While at it switched to clk_hw_register() instead of clk_register() as this has been marked as deprecated interface. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzg2l-cpg.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 04b78064d4e0..91cf972a20c3 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1023,6 +1023,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, struct clk_init_data init; const char *parent_name; struct pll_clk *pll_clk; + int ret; parent = clks[core->parent & 0xffff]; if (IS_ERR(parent)) @@ -1045,7 +1046,11 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, pll_clk->priv = priv; pll_clk->type = core->type; - return clk_register(NULL, &pll_clk->hw); + ret = devm_clk_hw_register(dev, &pll_clk->hw); + if (ret) + return NULL; + + return pll_clk->hw.clk; } static struct clk @@ -1337,6 +1342,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, struct clk *parent, *clk; const char *parent_name; unsigned int i; + int ret; WARN_DEBUG(id < priv->num_core_clks); WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); @@ -1380,10 +1386,11 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, clock->priv = priv; clock->hw.init = &init; - clk = clk_register(NULL, &clock->hw); - if (IS_ERR(clk)) + ret = devm_clk_hw_register(dev, &clock->hw); + if (ret) goto fail; + clk = clock->hw.clk; dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); priv->clks[id] = clk;