From patchwork Tue Jul 2 09:46:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13719330 X-Patchwork-Delegate: kieran@bingham.xyz Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 19EA213D8BA; Tue, 2 Jul 2024 09:47:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719913629; cv=none; b=j7toOmGID8Uvyt89j1B4CHBDqVV6zNr/xnjzRyFpq2rZMo8qzvkbuNn9jEKqxgUBYgjn/uAPHGtOpHN8L9P3NSVihiDk9SDKIZbvWRvKge+qiUxDVgG1OcvMQwAvzXPBC56/kC4FmmZYtDaerbaPZ1WL4+CE34EKy8YwuVQ6r3s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719913629; c=relaxed/simple; bh=6sNXErYGiELb7Mk0y+DGkEkaGdhlhJdxwEZ5Z0L9Gd8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Mc62/ava+wDyFaxaUkUInBrZZLGr3jCI/8B5f8xmjt/OWEiR/Ff0AOtOa56zibmIInWkg/a/8mU56AXsJnfNY+Qc2EKxYROuebE5I4lvBTCYFEkrnCpmQ4H9czNoL20nWWY/3LoFA1scjC3ytq0+r6U8beC8CX3a1GT2UdzxX5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.09,178,1716217200"; d="scan'208";a="213970948" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 02 Jul 2024 18:47:07 +0900 Received: from localhost.localdomain (unknown [10.226.93.72]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 24FF8400C9ED; Tue, 2 Jul 2024 18:47:01 +0900 (JST) From: Biju Das To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter Cc: Laurent Pinchart , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 5/9] drm: renesas: rz-du: Add RZ/G2UL DU Support Date: Tue, 2 Jul 2024 10:46:15 +0100 Message-ID: <20240702094630.41485-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240702094630.41485-1-biju.das.jz@bp.renesas.com> References: <20240702094630.41485-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The LCD controller is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). It has DPI interface and supports a maximum resolution of WXGA along with 2 RPFs to support the blending of two picture layers and raster operations (ROPs). The DU module is connected to VSPD. Add RZ/G2UL DU support. Signed-off-by: Biju Das --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 9 ++++++++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 11 +++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c index 6e7aac6219be..b1812f947252 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c @@ -28,6 +28,7 @@ #include "rzg2l_du_vsp.h" #define DU_MCR0 0x00 +#define DU_MCR0_DPI_OE BIT(0) #define DU_MCR0_DI_EN BIT(8) #define DU_DITR0 0x10 @@ -216,9 +217,15 @@ static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rcrtc) static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start) { + struct rzg2l_du_crtc_state *rstate = + to_rzg2l_crtc_state(rcrtc->crtc.state); struct rzg2l_du_device *rcdu = rcrtc->dev; + u32 val = DU_MCR0_DI_EN; - writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0); + if (rstate->outputs == BIT(RZG2L_DU_OUTPUT_DPAD0)) + val |= DU_MCR0_DPI_OE; + + writel(start ? val : 0, rcdu->mmio + DU_MCR0); } static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c index e5eca8691a33..34534441b7ec 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -25,6 +25,16 @@ * Device Information */ +static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = { + .channels_mask = BIT(0), + .routes = { + [RZG2L_DU_OUTPUT_DPAD0] = { + .possible_outputs = BIT(0), + .port = 1, + }, + }, +}; + static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { .channels_mask = BIT(0), .routes = { @@ -40,6 +50,7 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { }; static const struct of_device_id rzg2l_du_of_table[] = { + { .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info }, { .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info }, { /* sentinel */ } };