diff mbox series

[3/5] arm64: dts: renesas: r9a07g054(l1): Correct GICD and GICR sizes

Message ID 20240725133932.739936-4-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series arm64: dts: renesas: Correct GICD and GICR sizes | expand

Commit Message

Lad, Prabhakar July 25, 2024, 1:39 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The RZ/V2L SoC is equipped with the GIC-600. The GICD + GICDA is 128kB,
and the GICR is 128kB per CPU.

Fixes: 7c2b8198f4f32 ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi   | 4 ++--
 arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 5 +++++
 2 files changed, 7 insertions(+), 2 deletions(-)

Comments

Biju Das July 26, 2024, 5:19 a.m. UTC | #1 
Hi Prabhakar,

Thanks for the patch.

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Thursday, July 25, 2024 2:40 PM
> Subject: [PATCH 3/5] arm64: dts: renesas: r9a07g054(l1): Correct GICD and GICR sizes
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> The RZ/V2L SoC is equipped with the GIC-600. The GICD + GICDA is 128kB, and the GICR is 128kB per
> CPU.
> 
> Fixes: 7c2b8198f4f32 ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r9a07g054.dtsi   | 4 ++--
>  arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 5 +++++
>  2 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> index 1de2e5f0917d..8a9b61bd759a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> @@ -1051,8 +1051,8 @@ gic: interrupt-controller@11900000 {
>  			#interrupt-cells = <3>;
>  			#address-cells = <0>;
>  			interrupt-controller;
> -			reg = <0x0 0x11900000 0 0x40000>,
> -			      <0x0 0x11940000 0 0x60000>;
> +			reg = <0x0 0x11900000 0 0x20000>,

Can we update GIC-600 in[1]  based on [2] to avoid ABI breakage
in future?

IIC, As per [2], this patch series removes section GICT(GIC trace and debug page)
and GICP(GIC PMU) and [1] does not mention first reg is for GICD + GICA.
However, it mentions, it is for GICD.

reg:
    description: |
      Specifies base physical address(s) and size of the GIC
      registers, in the following order:
      - GIC Distributor interface (GICD)
      - GIC Redistributors (GICR), one range per redistributor region
      - GIC CPU interface (GICC)
      - GIC Hypervisor interface (GICH)
      - GIC Virtual CPU interface (GICV)

[1] https://elixir.bootlin.com/linux/v6.10.1/source/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

[2] https://developer.arm.com/documentation/100336/0106/programmer-s-model/the-gic-600-registers/register-map-pages?lang=en


Cheers,
Biju


> +			      <0x0 0x11940000 0 0x40000>;
>  			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>  		};
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
> b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
> index d85a6ac0f024..5c0f6c5d165e 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
> @@ -16,3 +16,8 @@ cpus {
>  		/delete-node/ cpu@100;
>  	};
>  };
> +
> +&gic {
> +	reg = <0x0 0x11900000 0 0x20000>,
> +	      <0x0 0x11940000 0 0x20000>;
> +};
> --
> 2.34.1
Lad, Prabhakar July 29, 2024, 11:36 a.m. UTC | #2 
Hi Biju,

On Fri, Jul 26, 2024 at 6:19 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Thursday, July 25, 2024 2:40 PM
> > Subject: [PATCH 3/5] arm64: dts: renesas: r9a07g054(l1): Correct GICD and GICR sizes
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The RZ/V2L SoC is equipped with the GIC-600. The GICD + GICDA is 128kB, and the GICR is 128kB per
> > CPU.
> >
> > Fixes: 7c2b8198f4f32 ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC")
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r9a07g054.dtsi   | 4 ++--
> >  arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 5 +++++
> >  2 files changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> > index 1de2e5f0917d..8a9b61bd759a 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> > @@ -1051,8 +1051,8 @@ gic: interrupt-controller@11900000 {
> >                       #interrupt-cells = <3>;
> >                       #address-cells = <0>;
> >                       interrupt-controller;
> > -                     reg = <0x0 0x11900000 0 0x40000>,
> > -                           <0x0 0x11940000 0 0x60000>;
> > +                     reg = <0x0 0x11900000 0 0x20000>,
>
> Can we update GIC-600 in[1]  based on [2] to avoid ABI breakage
> in future?
>
Sure will do.

Cheers,
Prabhakar

> IIC, As per [2], this patch series removes section GICT(GIC trace and debug page)
> and GICP(GIC PMU) and [1] does not mention first reg is for GICD + GICA.
> However, it mentions, it is for GICD.
>
> reg:
>     description: |
>       Specifies base physical address(s) and size of the GIC
>       registers, in the following order:
>       - GIC Distributor interface (GICD)
>       - GIC Redistributors (GICR), one range per redistributor region
>       - GIC CPU interface (GICC)
>       - GIC Hypervisor interface (GICH)
>       - GIC Virtual CPU interface (GICV)
>
> [1] https://elixir.bootlin.com/linux/v6.10.1/source/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
>
> [2] https://developer.arm.com/documentation/100336/0106/programmer-s-model/the-gic-600-registers/register-map-pages?lang=en
>
>
> Cheers,
> Biju
>
>
> > +                           <0x0 0x11940000 0 0x40000>;
> >                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> >               };
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
> > b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
> > index d85a6ac0f024..5c0f6c5d165e 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
> > @@ -16,3 +16,8 @@ cpus {
> >               /delete-node/ cpu@100;
> >       };
> >  };
> > +
> > +&gic {
> > +     reg = <0x0 0x11900000 0 0x20000>,
> > +           <0x0 0x11940000 0 0x20000>;
> > +};
> > --
> > 2.34.1
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 1de2e5f0917d..8a9b61bd759a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -1051,8 +1051,8 @@  gic: interrupt-controller@11900000 {
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 			interrupt-controller;
-			reg = <0x0 0x11900000 0 0x40000>,
-			      <0x0 0x11940000 0 0x60000>;
+			reg = <0x0 0x11900000 0 0x20000>,
+			      <0x0 0x11940000 0 0x40000>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
index d85a6ac0f024..5c0f6c5d165e 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
@@ -16,3 +16,8 @@  cpus {
 		/delete-node/ cpu@100;
 	};
 };
+
+&gic {
+	reg = <0x0 0x11900000 0 0x20000>,
+	      <0x0 0x11940000 0 0x20000>;
+};