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[5/5] arm64: dts: renesas: r9a07g044c1: Correct GICD and GICR sizes

Message ID 20240725133932.739936-6-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series arm64: dts: renesas: Correct GICD and GICR sizes | expand

Commit Message

Lad, Prabhakar July 25, 2024, 1:39 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The RZ/G2LC SoC is equipped with the GIC-600. The GICD + GICDA is 128kB,
and the GICR is 128kB per CPU.

Fixes: 3a3c2a48d8c6b ("arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 5 +++++
 1 file changed, 5 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
index 56a979e82c4f..18f092c4090c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
@@ -17,6 +17,11 @@  cpus {
 	};
 };
 
+&gic {
+	reg = <0x0 0x11900000 0 0x20000>,
+	      <0x0 0x11940000 0 0x20000>;
+};
+
 &soc {
 	/delete-node/ ssi@1004a800;
 	/delete-node/ serial@1004c800;