diff mbox series

[RFT,6/6] arm64: dts: r8a779h0-gray-hawk-single: Add TPU support

Message ID 20240725194906.14644-14-wsa+renesas@sang-engineering.com (mailing list archive)
State Under Review
Delegated to: Geert Uytterhoeven
Headers show
Series PWM & TPU patches for V4M | expand

Commit Message

Wolfram Sang July 25, 2024, 7:49 p.m. UTC
This patch enables TPU channel 1 for the GrayHawk board. Only for
testing, not for upstream.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 .../boot/dts/renesas/r8a779h0-gray-hawk-single.dts   | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Geert Uytterhoeven July 29, 2024, 6:52 p.m. UTC | #1
Hi Wolfram,

On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> This patch enables TPU channel 1 for the GrayHawk board. Only for
> testing, not for upstream.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
> @@ -223,6 +223,11 @@ scif_clk2_pins: scif-clk2 {
>                 groups = "scif_clk2";
>                 function = "scif_clk2";
>         };
> +
> +       tpu_pin: tpu {
> +               groups = "tpu_to1";

sh-pfc e6050000.pinctrl: invalid group "tpu_to1" for function "tpu"

This group does not exist. I assume you meant "tpu_to1_a"?

> +               function = "tpu";
> +       };
>  };
>
>  &pwm1 {
> @@ -279,3 +284,10 @@ &scif_clk {
>  &scif_clk2 {
>         clock-frequency = <24000000>;
>  };
> +
> +&tpu {
> +       pinctrl-0 = <&tpu_pin>;
> +       pinctrl-names = "default";
> +
> +       status = "okay";
> +};

Both tpu_to1(_a) and tpu_to2(_a) are available on CN3004, but I didn't
see any PWM signals on pins 10 and 12.  To be investigated further..

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Wolfram Sang July 29, 2024, 7:05 p.m. UTC | #2
> > +       tpu_pin: tpu {
> > +               groups = "tpu_to1";
> 
> sh-pfc e6050000.pinctrl: invalid group "tpu_to1" for function "tpu"
> 
> This group does not exist. I assume you meant "tpu_to1_a"?

Probably. I did test this via remote, though. Sorry, I assume this
hotfix got lost because the non-working pin got me distracted.

> Both tpu_to1(_a) and tpu_to2(_a) are available on CN3004, but I didn't
> see any PWM signals on pins 10 and 12.  To be investigated further..

I still assume they are driven low by something else. GPIO neither works
on these pins.
Geert Uytterhoeven July 30, 2024, 6:54 a.m. UTC | #3
Hi Wolfram,

On Mon, Jul 29, 2024 at 9:05 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> > > +       tpu_pin: tpu {
> > > +               groups = "tpu_to1";
> >
> > sh-pfc e6050000.pinctrl: invalid group "tpu_to1" for function "tpu"
> >
> > This group does not exist. I assume you meant "tpu_to1_a"?
>
> Probably. I did test this via remote, though. Sorry, I assume this
> hotfix got lost because the non-working pin got me distracted.
>
> > Both tpu_to1(_a) and tpu_to2(_a) are available on CN3004, but I didn't
> > see any PWM signals on pins 10 and 12.  To be investigated further..
>
> I still assume they are driven low by something else. GPIO neither works
> on these pins.

Indeed, I had tried using GP2_07 as remote-wake-up before, and that
also didn't work. The failing CANFD pins (still to be checked with
the scope) are also from bank 2, coincidence?

Keys (bank 5) and LEDs (bank 7) do work. I assume audio (bank0/1)
works, too.  I had briefly tried replacing i2c0 by i2c-gpio (bank 4),
and that also failed.

Perhaps there's a mistake in the register addresses for bank 2
(and bank 4?) in the PFC driver, or in the documentation?

Gr{oetje,eeting}s,

                        Geert
Wolfram Sang July 30, 2024, 9:40 a.m. UTC | #4
> Perhaps there's a mistake in the register addresses for bank 2
> (and bank 4?) in the PFC driver, or in the documentation?

That would be way better than pins somehow wired to low and being
unusable on the board. I am keeping fingers crossed.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
index 62878120673d..86d17950c017 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
@@ -223,6 +223,11 @@  scif_clk2_pins: scif-clk2 {
 		groups = "scif_clk2";
 		function = "scif_clk2";
 	};
+
+	tpu_pin: tpu {
+		groups = "tpu_to1";
+		function = "tpu";
+	};
 };
 
 &pwm1 {
@@ -279,3 +284,10 @@  &scif_clk {
 &scif_clk2 {
 	clock-frequency = <24000000>;
 };
+
+&tpu {
+	pinctrl-0 = <&tpu_pin>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};